Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-04
2004-07-06
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S775000
Reexamination Certificate
active
06759296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory cell. More particularly, the invention relates to a method of manufacturing a flash memory cell capable of improving a retention characteristic and preventing movement of threshold voltage control ions, in a way that a stack gate in which a floating gate and a control gate are stacked is formed at a given region of a semiconductor substrate, and a rapid thermal nitrification process is then performed to form a nitride film at the side of the stack gate and over the semiconductor substrate.
2. Description of the Prior Art
In a flash memory device having a gate structure in which a floating gate and a control gate are isolated by a dielectric film, electric charges are stored at the floating gate using a hot carrier injection. The floating gate formed of a polysilicon film, however, has a retention fail problem by which the stored charges could not be retained due to variation in a wide range of temperature and the operating voltage.
The retention fail problem is usually generated by defective oxide film. The defective oxide film is mainly generated by the leakage of electrons due to reduction in the height of an interface barrier. Also, the leakage of the electrons is mainly generated by etching damage of an ONO film used as a dielectric film after the etch process for forming an electrode. In order to overcome this etch damage, an oxidization process using a high temperature thermal process is implemented. In addition, an ion implantation process for forming a junction region is implemented after the oxidization process.
However, during the ion implantation process, the quality of a gate oxide film is degraded by charged dopant since ions are implanted into the oxide film formed on the entire surfaces of the electrode. Further, as the junction region is increased by the oxidization process, the program speed and cell current are reduced in a flash memory device in which a program is performed through injection of large amount of hot carriers.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a flash memory cell capable of improving a retention characteristic.
Another object of the present invention is to provide a method of manufacturing a flash memory cell by which the program speed and the cell current are not reduced.
Still another object of the present invention is to provide a method of manufacturing a flash memory cell in which the threshold voltage is not varied by preventing movement of threshold voltage control ions.
According to the present invention, in order to solve a problem that the quality of a dielectric film having a lower oxide film, a nitride film and an upper oxide film is degraded due to etching damage when an etch process for forming an electrode, a nitride film is formed by a rapid thermal nitrification process. Further, in order to solve a problem that the quality of the gate electrode is degraded due to implantation of an impurity ion into an oxide film that is formed around a gate electrode by a common oxidization process during an ion implantation process for forming a junction region, a thinly formed nitride film is used as a barrier layer.
In order to accomplish the above object, a method of manufacturing a flash memory cell according to the present invention, is characterized in that it comprises the steps of stacking a tunnel oxide film, a first polysilicon film, a dielectric film, a second polysilicon film and a tungsten silicide film at a given regions of a semiconductor substrate to form a stack gate in which a floating gate and a control gate are stacked; forming a nitride film at the side of the stack gate and on the semiconductor substrate by means of a rapid thermal nitrification process; and forming a junction region at a given region of the semiconductor substrate by means of an impurity ion implantation process.
REFERENCES:
patent: 5460992 (1995-10-01), Hasegawa
patent: 2003/0003656 (2003-01-01), Dong et al.
patent: 2001-61403 (2001-07-01), None
Kwak Noh Yeal
Park Sang Wook
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Le Dung A.
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