Semiconductor device with deep trench isolation and method...

Details Semiconductor device with deep trench isolation and method... Semiconductor device with deep trench isolation and method...

2002-11-19

2004-05-11

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S241000, C438S242000, C438S268000, C438S244000, C438S248000, C438S387000, C438S391000

Reexamination Certificate

active

06734059

ABSTRACT:

BACKGROUND OF THE INVENTION
Semiconductor devices are employed in various systems in a wide variety of applications. An important type of semiconductor device used as a memory is the dynamic random access memory (“DRAM”). DRAM is extensively used for memory in computers. A single DRAM memory cell may include a capacitor and a transistor, each formed in a semiconductor substrate. The capacitor stores a charge representing a data value. The transistor allows the data valve to be written to the capacitor, read from the capacitor or refreshed. A series of DRAM memory cells is typically arranged in an array.
More DRAM cells can be arranged onto a semiconductor chip by reducing the surface area of the capacitor and/or the transistor thus resulting in greater memory capacity for the chip. A method of minimizing the surface area of a DRAM cell is to construct the components vertically, i.e., where a semiconductor device includes components formed in several layers. One way to accomplish such vertical construction involves forming a trench in a semiconductor substrate. For example, a dielectric film may be deposited on the sides of the trench and layers of conductive, semiconductive and/or insulative material are then deposited in the trench. Each layer may be etched so as to have a desired shape and/or size. The steps of etching and depositing new material may be repeated until the desired component, e.g., a vertical DRAM memory cell is formed.
Preferably, the capacitor is fabricated in a lower portion of the trench and at least part of the transistor is formed over the capacitor in an upper portion of the trench. The transistor may comprise source, gate and drain regions where the source is connected to a storage node of the capacitor, the drain is connected to a bit line, and the gate connected to a word line.
FIG. 1
illustrates a conventional DRAM memory cell
400
including a capacitor
410
and a transistor
420
. The capacitor
410
includes a first electrode
412
and a second electrode
414
. Typically, a dielectric material (not shown) is disposed between the electrodes. The transistor
420
includes a source (or drain)
422
connected to the second electrode
414
. The transistor
420
also includes a drain (or source)
424
connected to a bit line
432
, as well as a gate
426
connected to a word line
430
. The data may be refreshed, read from, or written to the capacitor
410
of each memory cell of the memory array by the bit lines
432
and the word lines
430
.
As an example, the memory cell array may be arranged in rows and columns. A row may be connected to one bit line
432
, and a column may be connected to one word line
430
. A specific memory cell in the array is accessed by selecting the appropriate bit line
432
and word line
430
. The data may be refreshed, read from, or written to the capacitor by applying appropriate voltages to the bit line
432
and/or the word line
430
.
The bit line
432
may be connected to the drain (or source)
424
by a bit line contact. The word line
430
may be connected to the gate
426
by a word line contact, or the gate
426
itself may serve as the word line
430
. As the surface area of the memory cell decreases, the bit line contact and the gate/word line contact may be positioned closer together. By way of example only, using current fabrication techniques, the bit line contact and the gate/word line contact may be separated by 20-30 nm. The closer positioning of the bit line contact and the gate/word line contact may cause a short circuit or induce cross-talk between the components. This problem may occur due to device fabrication errors such as misalignment, over-etching or structural defects. For example, material layers are typically patterned by depositing a masking layer over the material layer and patterning the masking layer to expose portions of the material layer which are removed while other portions are covered. Then, a new material layer may be deposited and similarly patterned. If the masking layers are misaligned with respect to one another, the upper material layer may be located incorrectly, i.e., misaligned, thereby damaging or rendering the semiconductor device inoperable. Similarly, over-etching an exposed portion of the layer may damage the material layer or another layer and may lead to a short circuit between nearby components. To prevent such short circuits or cross-talk between the bit line contact and the gate/word line contact, isolation may be employed.
A known isolation technique requires a first spacer in the trench followed in a later processing step with another spacer surrounding the gate region. The first spacer is commonly referred to as a deep trench spacer, DT top spacer or DT spacer.
FIGS. 2
to
4
illustrate an example of a typical nitride spacer isolation process. As will become evident, such nitride spacer isolation may not prevent a short circuit or cross-talk in many situations.
Prior to the step illustrated in
FIG. 2
, a trench was formed in semiconductor substrate
100
having a surface
102
. A trench top oxide (“TTO”)
110
was formed in a lower portion of the trench to, e.g., isolate a capacitor (not shown) within the trench from a transistor which will be formed in an upper portion of the trench. The capacitor is commonly known as a trench capacitor. A gate oxide
116
lines sidewalls
114
of the trench. On either side of the sidewalls
114
are source (drain) regions
144
. Within the trench is a gate material
118
and a gate stud
130
. A gate conductor
150
connects to the gate stud
130
, and is protected by a silicate
172
and a nitride cap
174
. A screen oxide
140
is disposed over the source (drain) regions
144
. The screen oxide
140
also partly encloses a nitride spacer
142
. A nitride liner
146
is formed over the screen oxide
140
and the nitride spacer
142
. An array top oxide (“ATO”)
148
is formed over the nitride liner
146
. The processes of forming these elements are well known to those skilled in the art.
FIG. 2
illustrates the result of a processing step after the gate conductor
150
, the silicate
172
and the nitride cap
174
have been deposited over the gate stud
130
, the nitride spacer
142
and the ATO
148
. The gate conductor
150
, the silicate
172
and the nitride cap
174
are patterned and etched to a desired shape and size. As part of the etching process, a portion of the gate stud
130
is removed, typically by an anisotropic etch selective to oxide and nitride, leaving a recess
152
in the gate region.
After the recess
152
is formed, a gate spacer
160
, also known as a gate conductor spacer or GC spacer is formed, as shown in FIG.
3
. The gate spacer
160
is typically a nitride that is deposited over the wafer and covers the exposed surfaces. During deposition, the gate spacer
160
folds back on itself as it fills the recess
152
. Because of the nature of the deposition process, a seam or void
162
is typically formed as well.
FIG. 4
illustrates a further fabrication step after a bit line
178
is formed. An isolating material
176
, such as borophosphosilicate glass (BPSG), separates the device from other components on the wafer, such as the bit line
178
. The bit line
178
connects to the source region
144
through a bit line contact
180
. During processing steps such as spacer etch-back, it is difficult to maintain a uniform thickness of the gate spacer
160
. Furthermore, the seam or void
162
enhances the potential for over etching the bit line contact
180
, thus shorting the bit line contact
180
to the device. In particular, while the bit line etching process is typically selective to nitride, i.e., the process etches other materials more rapidly than it etches nitride, the process may rapidly etch through the seam or void
162
and provide direct contact (“punch-through”) between the bit line contact
180
and the gate material
118
.
Therefore, a need exists for an improved isolation technique which provides more robust protection. The improved isolation technique of the present inventio

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