Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-21
2004-09-28
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S239000
Reexamination Certificate
active
06797554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to methods of manufacturing integrated circuits comprising MOS transistors together with passive elements such as capacitors and resistors.
2. Description of Related Art
Concomitant with recent trends toward the miniaturization of semiconductor devices, resistance of a diffusion region in the lateral direction tends to increase with the decreases in depth of a p-n junction. For example, in MOS transistors, as source and drain regions become shallower in compliance with the reduction of the gate length, the resistances of the source and drain regions increase. As a result, it becomes difficult to form high-speed transistors.
Accordingly, silicidation techniques in which silicide films are formed on source and drain regions for decreasing the resistance thereof are widely used.
Of various silicidation techniques, the most widely used technique is a so-called self align silicide (salicide) technique. In this technique, after a refractory metal film of Ti or the like is deposited over the entire surface of a semiconductor substrate having source and drain regions and a gate electrode of a MOS transistor, the substrate is heated. A silicidation reaction is carried out only on the source and drain regions and the gate electrode, at which silicon surfaces are exposed. As a result, silicide films are selectively formed only on the source and drain regions and the gate electrode.
On the other hand, a transistor used for an input/output circuit may not be silicided in some cases, for example, to keep a required ESD tolerance. In such cases, after covering transistors which are not silicided with an insulating film (salicide block film), only the remaining uncovered transistors are silicided.
Conventionally, in a CMOS (complementary MOS) process including a step of forming a self-align silicide as described above, methods in which passive elements such as a capacitor element and a resistor element are formed together with MOS transistors have been proposed. In particular, in integrated circuits used for analog applications, those passive elements mentioned above have been frequently used.
For example, U.S. Pat. No. 5,736,421, hereby incorporated by reference in its entirety, discloses a method in which an insulating film used for a capacitor is also used as a salicide block film or sidewall spacers of a MOS transistor. In addition, U.S. Pat. No. 5,780,333, hereby incorporated by reference in its entirety, discloses a method in which an insulating film used for a capacitor and an upper electrode of the capacitor are simultaneously patterned. Various modifications of these methods are also disclosed in, for example, U.S. Pat. Nos. 5,924,011, 6,180,462, 6,204,105, and 6,246,084, hereby incorporated by reference in their entireties.
However, according to the method disclosed in U.S. Pat. No. 5,736,421, the upper electrode of the capacitor is formed after the capacitor insulating film is patterned. Accordingly, the capacitor insulating film may be contaminated or damaged during the patterning. Specifically, organic materials contained in the resist used in the patterning may contaminate the insulating film. Etching or ashing treatment in the patterning may also damage the insulating film. Therefore, the electric properties of the capacitor may be inferior.
In addition, according to the method disclosed in U.S. Pat. No. 5,780,333, the insulating film can be used only as the capacitor insulating film, because it is patterned simultaneously with the upper electrode. Therefore, another insulating film must be formed and then patterned in order to form a salicide block film or sidewall spacers, and therefore, the number of steps is increased.
SUMMARY OF THE INVENTION
In consideration of the problems described above, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit in which passive elements having superior electrical properties can be formed using an efficient process.
According to an aspect of this invention, a first exemplary method of manufacturing a semiconductor integrated circuit includes providing a semiconductor substrate having gate electrodes of a first and a second transistor and a lower electrode of a capacitor over a surface of the semiconductor substrate. The surface of the semiconductor substrate has source and drain regions of the first and the second transistors on respective first and second sides of each gate electrode.
The first exemplary method also includes forming an insulating film over the surface of the semiconductor substrate having the gate electrodes and the lower electrode, and forming an upper electrode of the capacitor over the lower electrode. The upper electrode is separated from the lower electrode by the insulating film.
The first exemplary method further includes removing selected parts of the insulating film after forming the upper electrode. The insulating film is removed to expose at least the source and drain regions of the second transistor while retaining remaining parts of the insulating film including those covering the source and drain regions of the first transistor.
Finally, the first exemplary method includes selectively forming silicide films on the exposed source and drain regions of the second transistor.
Preferably, forming a second conductive material film on an entire surface of the insulating film and patterning the second conductive material film forms the upper electrode.
According to the first exemplary method, parts of the insulating film are used as a capacitor insulation film, and other parts of the insulating film are used as a salicide block film. Accordingly, a semiconductor integrated circuit having silicided and non-silicide transistors and a capacitor is efficiently formed over a surface of the same semiconductor substrate by a process flow including a small number of manufacturing steps.
In addition, after the insulating film used as the capacitor insulating film is formed, the conductive material film used as the upper electrode is then formed before patterning the insulating film. Accordingly, the capacitor insulating film is not contaminated, or damaged. Therefore, a capacitor having superior electrical properties can be formed.
As a modification of the first exemplary method, the semiconductor substrate has a resistor in addition to the gate electrodes and the lower electrode. The insulating film is formed over the surface of the semiconductor substrate having the resistor in addition to the gate electrodes and the lower electrode, and a part of the insulating film covering the resistor is retained in the removing step.
In this case, a resistor can be efficiently formed on a surface of the same semiconductor substrate by a process flow including a small number of manufacturing steps.
According to another aspect of this invention, a second exemplary method of manufacturing a semiconductor integrated circuit includes providing a semiconductor substrate having gate electrodes of a first and a second transistor and a lower electrode of a capacitor over a surface of the semiconductor substrate. The surface of the substrate has source and drain regions of the first and the second transistors on respective sides of each gate electrode. The surface of the substrate also has a resistor-forming region.
The second exemplary method also includes forming a first insulating film over the surface of the semiconductor substrate having the gate electrodes, the lower electrode, and the resistor forming region, and forming an upper electrode of the capacitor above the lower electrode and a resistor over the resistor-forming region. The upper electrode is separated from the lower electrode by the first insulating film.
The second exemplary method further includes forming a second insulating film over the surface of the semiconductor substrate having the upper electrode and the resistor, and removing selected parts of the first and the second insulating films. The first and the second insulating films are r
Kawasaki Microelectronics Inc.
Lee Hsien Ming
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