Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-04-27
2004-01-27
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S710000
Reexamination Certificate
active
06684355
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory testing apparatus and a memory testing method, and more specifically to the structure of a fail information memory in a memory testing apparatus and a memory testing method using a fail information memory.
In the prior art, a redundant design is adopted in a semiconductor memory in order to remedy the whole of a memory device from becoming defective because of one bit memory cell defect or one row or column defect.
Referring to
FIG. 1
, there is shown a block diagram of an example of a conventional memory of the redundant design. The shown memory is so configured that when a defective row or column within a memory cell array
200
of the semiconductor memory is accessed, a redundant row
203
or a redundant column
204
is selected in place of the defective row or column by a redundant X decoder
205
or a redundant Y decoder
206
, with the result that since the memory cell array
200
containing the defective row or column is remedied, the yield of production is elevated.
Explaining the semiconductor memory shown in
FIG. 1
, in the memory cell array
200
there is accessed a memory cell designated by a word line selected by an X decoder
201
, which receives and decodes an X address and selects a word line designated by the X address, and a digit line selected by a Y decoder
202
, which receives and decodes a Y address and selects a digit line designated by the Y address, by turning on a not-shown Y switch connected in series in the digit line designated by the Y address. In this access, if the memory cell designated within the memory cell array
200
is defective, the access to the designated memory cell is replaced by an access to a redundant cell included in the redundant row
203
or the redundant column
204
, by action of the redundant X decoder
205
or the redundant Y decoder
206
. Here, in order to distinguish the memory cells included in the memory cell array
200
from the redundant cells, each memory cell included in the memory cell array
200
will be called a “main cell”, and the memory cell array
200
will be called a “memory cell array” in this specification.
When a defective cell is detected at a wafer test in a semiconductor memory fabricating process, the redundant row or the redundant column is set by cutting off a fuse in a circuit provided in the semiconductor memory of the redundant design. Here, replacement of the defective cell by the redundant cell in the semiconductor memory of the redundant design is ordinarily executed by various methods, for example, the cutting-off of the fuse, a laser annealing diffusion, an EEPROM, a metal fuse, etc. However, since this does not have a direct relation to the subject of the present invention, further explanation will be omitted.
A memory tester used for detecting a defective in the semiconductor memory at the wafer test or at a final test after the semiconductor memory is assembled, includes a fail information memory for storing fail information.
In the wafer test, the fail information stored in the fail information memory of the memory tester is read out from the fail information memory, and is stored as a fail bit map information in a host computer of the memory tester. After the wafer test, in the semiconductor memory of the redundant design, the redundant row or the redundant column is set on the basis of the fail bit map by the fuse cutting-off or another means.
Referring to
FIG. 2
, there is shown a functional block diagram illustrating the construction of one example of a conventional memory tester. As shown in
FIG. 2
, the conventional memory tester includes a timing generator (TG)
100
for generating various timings including a timing of a test cycle, an edge timing of an applied waveform, a strobe timing of a comparator, and others, an algorithmic pattern generator (ALPG)
102
for generating various address patterns and data including a march, a galloping, and others, a programmable data selector (PDS)
103
for allocating a pattern supplied from the algorithmic pattern generator (ALPG)
102
to arbitrary pins on the basis of a test program, a formatter (FC)
104
for variably controlling the format of a waveform to be applied, a driver circuit
105
for applying an input pattern to input terminals of a device under test (DUT)
108
, a comparator circuit
106
for receiving and comparing output signals from the device under test (DUT)
108
, a digital comparator (DC)
107
for comparing the comparison result outputted from the comparator circuit
106
with a desired value pattern, and a fail information memory
101
receiving the comparison result outputted from the digital comparator (DC)
107
for storing the fail information for each test cycle and in accordance with a test address.
Referring to
FIG. 3
, there is shown a block diagram showing the construction of one channel of a comparison function in the conventional memory tester shown in
FIG. 2
, although the comparison function actually includes a plurality of channels. In
FIG. 8
, a voltage outputting circuit (VO)
109
generates a reference voltage to be compared with the output signal of the device under test (DUT), specifically, a high level reference voltage and a low level reference voltage. The comparator
106
compares the output signal of the device under test (DUT), with the reference voltages supplied from the voltage outputting circuit (VO)
109
, and outputs the result of the comparison to the digital comparator (DC)
107
. The digital comparator (DC)
107
is controlled by the strobe signal supplied from the timing generator (TG)
100
to compare the comparison result outputted from the comparator
106
with an expect value data generated in the algorithmic pattern generator (ALPG)
102
and pin-allocated by the programmable data selector (PDS)
103
.
As shown in
FIG. 3
, the fail information memory
101
is provided for each comparator channel, and when the result of the comparison executed in the digital comparator (DC)
107
shows a “fail”, the fail information is written into the fail information memory
101
in accordance with the address outputted from the algorithmic pattern generator (ALPG)
102
, namely, the reading address for the device under test when the “fail” occurs.
However, a specific proposal and development have not yet been made in connection with the architecture of a memory tester having a fail information memory corresponding to the redundant cells in the semiconductor memory of the redundant design.
Here, consideration will be made on the case that the semiconductor memory of the redundant design is tested by use of the conventional memory tester mentioned above. In this case, the redundant cells in the semiconductor memory of the redundant design are tested (for example, after data is written to the redundant cells, data is read out from the redundant cells). If fail information of the redundant cells is written to a fail information memory, it is inevitably necessary to increase the memory capacity of the fail information memory. This is disadvantageous.
Now, this problem will be described in detail on the assumption that the fail information of the redundant cells in the device under test is written to a fail information memory of the existing memory tester.
Here, in the wafer test, an address space of the semiconductor memory of the redundant design, which is accessed by the memory tester by setting the semiconductor memory of the redundant design to a test mode, is composed of a combination of an address space of the main cell array and an address space of the redundant cell array. On the other hand, after shipment of a semiconductor memory product, since replacement of defective cells in the main cell array by redundant cells has been finished within the inside of the semiconductor memory, the address space of the semiconductor memory accessible to a user corresponds to the main cell array.
When the semiconductor memory of the redundant design shown in
FIG. 1
is tested by use of the conventional memory tester shown
Chung Phung M.
Dickstein Shapiro Morin & Oshinsky LLP.
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