Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-04-18
2004-07-27
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C327S165000
Reexamination Certificate
active
06768133
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a test method for a semiconductor device, and a tester for a semiconductor device. In particular, the present invention relates to a high-speed semiconductor device.
2. Background Art
After its fabrication, a semiconductor device is subjected to various tests such as timing tests and functional tests. Description will be made of a test method for a semiconductor device using a tester
101
with reference to FIG.
8
. As shown in the figure, a semiconductor device
105
to be tested, which is hereinafter referred to as a DUT (Device Under Test), is connected to the tester
101
in the test.
The tester
101
comprises a tester main unit
102
, a test head
103
, and a pin electronics card
104
. The tester main unit
102
generates a test pattern signal required as a test condition for the DUT
105
.
FIG. 8
shows the DUT
105
and the tester
101
disposed side by side, for convenience. In the actual test, however, the DUT
105
is stored in the test head
103
and tested.
FIG. 9
is a schematic diagram showing the configuration of the pin electronics card
104
. In the test, upon receiving a signal from the tester main unit
102
, a tester driver
111
of the pin electronics card
104
generates a test signal that is then applied to the DUT
105
. The response signal from the DUT
105
is received by a comparator
112
in the pin electronics card
104
, and the comparator
112
compares the signal with its expected value. Then, the tester
101
determines whether or not the DUT
105
operates as specified by its design.
However, as semiconductor devices have become complicated and their scale has increased, testing of semiconductor devices has become more and more difficult to carry out. Furthermore, since the operating speeds of the devices have been accelerated increasingly, a timing test for ensuring their high-speed operation requires very high timing accuracy.
To cope with such super-high-speed operation of the devices, a two-path system has been widely adopted in which an expensive high-precision tester is used only for a high-speed operation test and a tester of low precision is used for a low-speed test, specifically, a functional test, in order to reduce the cost. Recently, however, the speed of the devices has further increased, and will continue to increase in the future, requiring execution of a high-precision test on a super-high-speed device, which necessitates a more expensive tester. This makes it difficult to test the devices at a reasonable cost.
When checking a super-high-speed and large-scale semiconductor device by use of the conventional tester
101
shown in
FIG. 8
, it is necessary to replace the tester
101
with an expensive high-precision tester to test high-speed operation of the device even in the case where the two-path system is adopted. This means that as the speed of devices becomes higher, it is necessary to employ an expensive high-precision tester to enhance the test accuracy, putting a limit on reduction of the test cost.
One reason why the high-precision tester is expensive is that the tester
101
must include a plurality of high-precision pin electronics cards
104
. This is because it is necessary to provide a number of pin electronics cards
104
corresponding to the number of a plurality of output terminals included in the DUT
105
. In the conventional high-precision tester, for example, it is necessary to employ a number of pin electronics cards
104
equal to the number of the output terminals included in the DUT
105
, inevitably increasing the cost of the tester
101
.
SUMMARY OF THE INVENTION
In view of the foregoing, the present invention has been made, and it is an object of the present invention to provide a semiconductor device, a test method for a semiconductor device, and a tester for a semiconductor device that are able to realize a low-cost high-speed timing test.
According to one aspect of the present invention, a semiconductor device comprises a plurality of output terminals, a plurality of buffer circuits, and a delay means. Signals from an internal circuit are output through the output terminals. Each buffer circuit is provided between one of the plurality of output terminals and the internal circuit. The delay means is connected to a specific one of the plurality of buffer circuits. The delay means delays a signal from the internal circuit.
According to another aspect of the present invention, there is provided a method for testing a semiconductor device having a plurality of output terminals. The method comprises the following steps. A test signal is applied to the semiconductor device. An output signal from only a specific one of the plurality of output terminals delayed. Timing delay characteristics of the semiconductor device evaluated based on the delayed output signal.
According to another aspect of the present invention, there is provided a tester for a semiconductor device. The tester comprises a test signal applying means and a plurality of comparison means. The test signal applying means is for applying a test signal to a semiconductor device to be tested. The comparison means is for receiving a plurality of output signals which are output from the semiconductor device based on the test signal. Each comparison means compares the output signal with predetermined expected values. A specific one of the plurality of comparison means is higher than the other ones of the plurality of comparison means in capability of evaluating timing delay characteristics.
Since a delay means is provided in a specific buffer circuit to delay a signal from an internal circuit, it is possible to measure a delay time from an input test signal even when a high-speed device is tested. Thus, it is possible to evaluate the timing delay characteristics of a semiconductor device with high precision and thereby provide a highly reliable semiconductor device.
Since a specific comparison means is made higher than the other comparison means in the capability of evaluating timing delay characteristics, only one comparison means included in a tester need be of high-precision type to be able to perform a timing test and a functional test on a high-speed semiconductor device with high precision. Therefore, it is possible to considerably reduce the cost of the tester and perform a highly reliable test.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 6278128 (2001-08-01), Noji et al.
patent: 6469396 (2002-10-01), Kawai
McDermott Will & Emery LLP
Renesas Technology Corp.
Wille Douglas
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