Low clock swing latch for dual-supply voltage design

Details Low clock swing latch for dual-supply voltage design Low clock swing latch for dual-supply voltage design

2001-12-20

2004-07-13

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S190000, C365S189110, C365S227000, C326S081000, C326S080000

Reexamination Certificate

active

06762957

ABSTRACT:

FIELD
The present invention relates generally to latches, and more specifically to latches in dual-supply voltage designs.
BACKGROUND
Latch circuits are widely used to temporarily store data and transfer the data from one part of a circuit to another part of the circuit. Integrated circuits such as microprocessors and memory devices often include a number of latch circuits and typically have a single supply voltage. However, because of demand for longer battery life in ultra low-power microprocessors and other circuits, designers have proposed a concept of dual-supply voltages. It has been shown that a large percentage of the overall energy consumed in a synchronous microprocessor is due to the clocking. Therefore, if the clock signal swing can be reduced, there can be significant savings in energy as well.
FIG. 1A
shows a conventional latch
100
for use in a dual-supply circuit. Latch
100
receives an input signal Din and outputs an output signal Dout. Latch
100
has a data path that includes transistors P
1
and N
1
and an inverter I
1
. Latch
100
also has a feedback path that includes inverters I
2
and I
3
and transistors P
2
and N
2
. Clock signals CLK and CLK* control the data and feedback paths. An inverter I
4
receives the CLK signal and outputs the CLK* signal. Inverters I
1
, I
2
, and I
3
connect to a supply voltage Vcch and inverter I
4
connects to a supply voltage Vccl; Vcch is greater than Vccl. The Din and Dout signals are Vcch signals. The CLK and CLK* signals are Vccl signals. A Vccl signal has a high potential level corresponding to Vccl; a Vcch signal has a high potential level corresponding to Vcch, which is greater than Vccl. Both Vccl and Vcch have the same low potential level, e.g., zero or ground.
When the CLK signal switches from zero to Vccl, the CLK* signal switches to zero. Transistor N
1
turns on fully and passes the Din signal to node A. Inverter I
1
receives the potential level at node A and produces an output signal Dout at the output node of the latch. Inverters I
2
and I
3
receives the potential level at node A and store it at node B. During this time, transistor N
2
turns off fully. However, if the data at node A from the current cycle is different from the data at node B from the previous cycle, transistor P
2
only turns off partially, leading to charge contention.
When the CLK signal switches from Vccl to zero, the CLK* signal switches to Vccl. Transistor N
1
turns off fully but transistor P
1
only turns off partially. Therefore, if the potential level of the Din signal is different from the potential level at node A, static power dissipation would occur. The charge contention and static power dissipation lead to poor performance.
FIG. 1B
shows another conventional latch
150
. Latch
150
includes internal nodes X and Y. Transistors M
1
and M
2
connect to nodes X and Y and to transistor M
3
and inverter IN
1
to allow node X or Y to discharge to ground, in response to a potential level of a clock signal CLK. Cross-coupled inverters IN
2
and IN
3
connect to node X and Y to operate as a feedback loop.
When the CLK signal switches from zero to Vccl, transistor M
3
turns on. Depending on the level of the Din signal, either node X or Y selectively discharges to ground through transistors M
1
and M
3
or M
2
and M
3
. Inverters IN
2
and IN
3
hold the Din signal as potential levels at nodes X and Y. Inverter IN
4
receives the potential level at node Y and produces an output signal Dout signal at the output node of the latch. As long as the CLK signal is at Vccl, latch
150
is transparent and the Din signal is available at the output of latch
150
as the Dout signal.
When the CLK signal switches from Vccl to zero, transistor M
3
turns off, stopping the effect of the Din signal on nodes X and Y. However, inverters IN
2
and IN
3
hold nodes X and Y at the previous potential level of the Din signal until the CLK signal switches to Vccl.
A problem arises when node X or Y discharges to ground but node X or Y holds an opposite potential level from the previous cycle. For example, when the CLK signal switches from zero to Vccl and the Din signal is at Vcch, transistor M
1
turns on and node X discharges to ground. However, if node X holds the Vcch potential, discharging to ground would cause a charge contention, leading to poor performance.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for an improved latch.


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