Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-05-20
2004-04-13
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S366000, C438S592000
Reexamination Certificate
active
06720226
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a silicide layer in its source/drain regions and also relates to a method for fabricating the device. The present invention more particularly relates to measures to reduce a junction leakage current.
Recently, as MISFETs included in an LSI chip have their sizes tremendously reduced and their operating speed increased, it has become increasingly necessary for the MISFETs to have their sizes further reduced in accordance with the scaling law. In particular, it has become more and more necessary to reduce the width of the sidewall on the gate electrode and a contact margin provided between the gate electrode and the source or drain region of the MISFETs. Also, for the purpose of reducing the resistivity of the source/drain regions, a process for forming a silicide in the surface regions of the source/drain regions and the gate electrode, i.e., a salicide (self-aligned silicide) process, has been adopted more and more often.
When such a salicide process is adopted, it is necessary to prevent the thickness of the sidewall from being reduced too much while a wet etching process is performed using hydrofluoric acid solution before a metal film for the salicide structure is deposited. For this purpose, a silicon nitride film with high resistibility to the wet etching process is generally used for the sidewall. It is also necessary to prevent the source/drain contact from being shortcircuited with the gate electrode or part of the semiconductor substrate located under the sidewall, e.g., extended or LDD (lightly doped drain) regions, even when the source/drain contact has overlapped with the gate electrode or sidewall. For this purpose, an insulating film to be deposited on the gate electrode and the sidewall are usually made of silicon nitride films with high resistibility to a dry etching process. However, it is known that if the silicon nitride film is deposited directly on the side faces of the gate electrode, the following problems will arise. Specifically, stress might be applied to the channel region of the semiconductor substrate from the silicon nitride film. Also, the durability of the gate insulating film to hot carriers decreases because of harmful effects caused by hydrogen atoms contained in the silicon nitride film. In addition, since the silicon nitride film has a high dielectric constant, the capacitance formed between the gate and the source or drain region might increase where the sidewall consists of the silicon nitride film alone. Thus, the operating speed of the circuit might decrease. To eliminate these problems, the sidewall generally has a double-layer structure made up of a nitride film and a silicon dioxide film, which is interposed between the nitride film and gate electrode and between the nitride film and semiconductor substrate.
In addition, MISFETs are also disposed for the I/O ports on the same semiconductor substrate. These MISFETs have a structure with no silicide layer formed in the source/drain regions so as to ensure sufficient durability for the gate oxide film and good electrostatic discharge (ESD) resistibility. That is to say, the single semiconductor substrate includes regions to be silicided and regions not to be silicided.
FIGS. 6A through 6E
are cross-sectional views showing a known method for fabricating a semiconductor device with a poly-metal gate structure. In
FIGS. 6A through 6E
, only an NMISFET region is illustrated. However, a PMISFET actually exists on another part of the substrate.
First, in the process step shown in
FIG. 6A
, silicon dioxide, n-polysilicon, metal and silicon nitride films are deposited in this order over a semiconductor substrate
101
. Then, a photolithographic process is performed to form a photoresist film as an etching mask over the silicon nitride film. Subsequently, the silicon nitride, metal, polysilicon and silicon dioxide films are patterned by an etching process using the photoresist film as a mask, thereby forming on-gate silicon nitride film
105
, upper gate electrode
104
of the metal film, lower gate electrode
103
of the polysilicon film and gate insulating film
102
. Thereafter, a photoresist film (not shown) is formed to cover a PMISFET region (now shown). Then, arsenic ions (As
+
), for example, are introduced into the NMISFET region of the semiconductor substrate
101
at a dose of about 5.0×10
14
atoms·cm
−2
with an accelerating voltage of about 10 keV applied and with the on-gate silicon nitride film
105
and gate electrodes
104
and
103
used as a mask. In this manner, n-type extended (or LDD) regions
106
are defined in the semiconductor substrate
101
.
Next, in the process step shown in
FIG. 6B
, a silicon dioxide film
107
and a silicon nitride film
108
are deposited in this order to thicknesses of about 20 nm and about 80 nm, respectively, over the substrate by an LPCVD (low-pressure chemical vapor deposition) process, for example.
Then, in the process step shown in
FIG. 6C
, the silicon nitride film
108
and silicon dioxide film
107
are etched back by an anisotropic etching process, thereby forming a nitride sidewall
108
a
and an L-sidewall
107
a
having an L-shaped cross section. Thereafter, arsenic ions, for example, are introduced into the semiconductor substrate
101
at a dose of 5.0×10
15
atoms·cm
−2
with an accelerating voltage of about 50 keV applied and with the on-gate silicon nitride film
105
, gate electrodes
104
and
103
and sidewalls
108
a
and
107
a
used as a mask. Subsequently, rapid thermal annealing is performed at a temperature of 1000° C. for 10 seconds. In this manner, n-type heavily doped source/drain regions
109
are defined in the semiconductor substrate
101
.
Next, in the process step shown in
FIG. 6D
, before a silicide layer is formed on the heavily doped source/drain regions
109
, the following process steps are performed to prevent the silicide layer from being formed in a region not to be silicided (not shown). Specifically, an antireactive silicon dioxide film is deposited by an LPCVD process, for example, to a thickness of about 50 nm over the substrate. Then, a photoresist film is formed on the antireactive silicon dioxide film so as to cover the region not to be silicided and expose the region to be silicided (e.g., the region shown in FIG.
6
D). By using this photoresist film as an etching mask, the antireactive silicon dioxide film is wet-etched by a buffered hydrofluoric acid solution diluted to 1:20, for example, for about 30 seconds. In this manner, part of the antireactive silicon dioxide film located over the region to be silicided is removed. In this case, to remove that part of the antireactive silicon dioxide film as much as possible, the antireactive silicon dioxide film is over-etched. However, as a result of this over-etching, the lower edge of the L-sidewall
107
a
sandwiched between the nitride sidewall
108
a
and semiconductor substrate
101
is partially etched. Thus, an oxide-removed region Rde is created as shown in FIG.
6
D.
Then, in the process step shown in
FIG. 6E
, the photoresist film is removed by a process such as ashing or RCA cleaning, during which a silicon dioxide film is formed on the surface of the silicon layer (such as the heavily doped source/drain regions
109
). Thus, the silicide dioxide film is wet-etched away by a hydrofluoric acid solution diluted to 1:100, for example. As a result of this process, the L-sidewall
107
a
is further etched. Subsequently, a Co film is deposited to a thickness of about 8 nm over the substrate and then annealed at a temperature of 550° C. for 60 seconds, for example, thereby allowing Co to react with Si at the interface between the silicon layer and Co film. As a result, a cobalt silicide (CoSi
2
) layer
111
is formed on the heavily doped source/drain regions
109
. Thereafter, non-reacted parts of the Co film are removed by a selective wet etching process.
By performing these process steps, the resultant device is i
Dang Phuc T.
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald T.
LandOfFree
Semiconductor device and method for facticating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for facticating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for facticating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3214514