Output circuit of semiconductor memory device

Details Output circuit of semiconductor memory device Output circuit of semiconductor memory device

1998-08-28

1999-08-17

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, 365203, 327 57, G11C 1604

Patent

active

059403314

ABSTRACT:
An output circuit of a semiconductor memory device is provided, which prevents a current from flowing through a pair of output transistors due to their ON-ON state. This output circuit is comprised of (a) first and second transfer gates for receiving first and second complementary read-bus data signals and for transferring the first and second read-bus data signals according to a transfer-gate control signal, (b) first and second latches for latching the first and second read-bus data signals transferred to first and second nodes, respectively, (c) a precharge signal generator for generating a precharge signal to precharge the first and second nodes to a same electric potential, (d) first and second transistor drivers for outputting first and second driving signals according to the first and second read-bus data signals latched at the first and second nodes, respectively, and (e) first and second complementary output transistors driven by the first and second driving signals outputted from the first and second drivers, respectively. The first and second nodes are respectively precharged to the same electric potentials by the precharge signal before the complementary first and second read-bus data signals are transferred by the first and second transfer gates and latched by the first and second latches at the first and second nodes, respectively.

REFERENCES:
patent: 5384735 (1995-01-01), Park et al.
patent: 5384736 (1995-01-01), Jung et al.
patent: 5444661 (1995-08-01), Matsui
patent: 5488581 (1996-01-01), Nagao et al.
patent: 5652724 (1997-07-01), Manning
patent: 5822254 (1998-10-01), Koshikawa et al.

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