Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2002-10-08
2004-09-28
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S694000
Reexamination Certificate
active
06797642
ABSTRACT:
BACKGROUND
1. Field of Invention
The present invention generally relates to semiconductor processing and, more particularly, to a method and structure for improving barrier layer adhesion.
2. Related Art
Current integrated circuits generally include various formations of multilevel metal structures that form a high-conductivity, thin-film network fabricated above the silicon surface to connect various active devices through specific electrical paths. During the formation of metal-to-metal and metal-to-silicon contact structures in this thin-film network, openings are etched in the dielectric layer that separates the substrate or underlying conductive thin film from the overlying conductive thin film. After openings for interconnect structures (lines and vias) have been etched through the dielectric, a diffusion barrier layer is commonly deposited over the dielectric to prevent intermixing or diffusion of interconnect material. A conductive material, such as copper, aluminum, or other metal, is then used to fill the opening and make a connection to the silicon substrate or underlying conductive thin film.
A problem that affects the electrical reliability of the metal layers is the adhesion between a dielectric layer and an adjoining barrier layer that insulates a metal layer. Poor barrier layer-to-dielectric layer adhesion could lead to delamination. Delamination occurs when a portion of the barrier layer peels apart or separates from the dielectric layer, which may cause problems when forming, filling, and electrically contacting a metal line. Thus, in the manufacture of semiconductor devices, it is important to have reliable barrier-to-dielectric layer adhesion.
Delamination of the barrier layer from the dielectric layer may occur for several reasons, including thermal stresses, intrinsic stresses of the film during deposition, etching chemistries, chemical-mechanical polish (CMP) forces applied on the films, and electrical cycling.
One reason that delamination occurs may be the processing which the layers are exposed to prior to the deposition of the barrier layer. For example, when forming vias to provide connection to copper wires, an argon sputter is typically performed as the first step prior to the barrier deposition over the via. The purpose of the argon sputter is to remove a copper oxide film from the copper below the via. Copper reacts with oxygen and easily forms a surface layer of high resistivity copper oxide when exposed to an oxygen rich atmosphere. This oxidation can occur when the wafers, just having the vias etched therein, are moved from an etch tool to a metallization tool. To minimize the resistance of the copper interconnect, the copper oxide layer must be removed, such as with the argon sputter. However, copper and copper oxide will be redeposited on the via sidewalls during the argon sputter creating the possibility of copper diffusing into the dielectric, poisoning it and degrading its electrical insulating capability. Such damage to the dielectric, whether in the field or on the sidewalls, can prevent adhesion to the damaged dielectric.
Another reason delamination may occur is from heat treatment steps during substrate processing. For example, an anneal step may be needed to repair damage to a substrate after a plasma processing step. Such heat cycles may cause the layers to change in stress characteristics or undergo chemical reactions that result in loss of adhesion properties, such as that which occurs between lower-k dielectrics and adjacent diffusion barrier material at high temperatures.
Therefore, what is needed is a method to improve adhesion of the barrier layer to the dielectric layer that can maintain the desired properties of the dielectric layer, such as the dielectric constant and other insulating properties, while remaining bonded during later planarization steps.
SUMMARY
The present invention provides a method for depositing a barrier material to form a barrier layer over an aperture structure etched through a dielectric layer, bombarding the barrier material with a plasma, and again depositing barrier material over the aperture structure to improve adhesion characteristics of the barrier layer.
In one embodiment of the present invention, a method to improve barrier layer adhesion comprises providing a semiconductor structure comprising a dielectric layer overlying a metal layer, etching an aperture through the dielectric layer to expose a portion of the metal layer, depositing a first barrier material to form a barrier layer over the dielectric layer and over the exposed portion of the metal layer, bombarding the barrier layer with a plasma, the bombarding leaving a portion of the barrier layer over a top surface of the dielectric layer, and depositing a second barrier material over the portion of the barrier layer and over the aperture.
In another embodiment, a first barrier material is deposited to form a barrier layer over the dielectric layer and over the exposed portion of the metal layer with the barrier layer having a greater thickness over the dielectric layer than over the exposed portion of the metal layer. The barrier layer is bombarded with an inert plasma to push barrier material into the dielectric layer with the bombarding leaving a portion of the barrier layer over a top surface of the dielectric layer.
Advantageously, the present invention allows for layers that remain bonded through CMP, improved critical fracture energy values that indicate improved adhesion between barrier layers and dielectric layers, and avoidance of dielectric poisoning.
This invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.
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Chu Karen
Danek Michal
Vijayendran Anil
Chen & Heid LLP
Geyer Scott B.
Kwok MacPherson
Novellus Systems Inc.
Park David S.
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