Method for fabricating a memory cell

Details Method for fabricating a memory cell Method for fabricating a memory cell

2003-02-28

2004-09-21

Nguyen, Cuong (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000

Reexamination Certificate

active

06794249

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to the field of electrically writable and erasable non-volatile flash memories. It describes a non-volatile memory cell which is constructed in accordance with the SONOS principle (semiconductor-oxide-nitride-oxide-semiconductor) and can be used in a virtual-ground NOR architecture.
Extremely small non-volatile memory cells are required for very large scale integration densities for multimedia applications. Ongoing development in semiconductor technology allows increasingly large storage capacities, which will very soon reach the gigabit range. However, while the minimum feature size, which is determined by lithography, continues to decrease, other parameters, such as for example the thickness of the tunnel oxide, can no longer be scaled accordingly. The associated reduction in the channel length in planar transistors with smaller features requires an increase in the channel doping, in order to avoid the occurrence of a punch-through between the source and the drain. This leads to an increase in the threshold voltage, which is usually compensated for by a reduction in the thickness of the gate oxide.
However, planar SONOS memory cells which can be programmed by channel-hot electrons and can be erased using hot holes (cf. Boaz Eitan U.S. Pat. No. 5,768,192, U.S. Pat. No. 6,011,725, WO 99/60631) require a control dielectric with a thickness which is equivalent to a gate oxide. However, this thickness cannot be reduced as desired without the number of program cycles which can be executed (the endurance of the memory cell) falling unacceptably. Therefore, a sufficiently great channel length to ensure that the dopant concentration in the channel does not have to be selected to be excessively high is required, since otherwise the threshold voltage rises too greatly.
The publication by J. Tanaka et al.: “A Sub-0.1 &mgr;m Grooved Gate MOSFET with High Immunity to Short-Channel Effects” in IEDM 93, pp. 537-540 (1993) describes a transistor on a p
+
substrate, in which the gate electrode is arranged in a trench between the n
+
-source region and the n
+
-drain region, so that in this way a curved channel region is formed in the substrate.
The publication by K. Nakagawa et al.: “A Flash EEPROM Cell with Self-Aligned Trench Transistor & Isolation Structure” in 2000 IEEE Symposium on VLSI Technology Digest of Technical Papers describes a transistor as a memory cell with a floating-gate electrode, which is arranged between the n
+
-source region and the n
+
-drain region, extending into a p-well of the substrate. Between the floating-gate electrode and the control-gate electrode there is a dielectric layer of an oxide-nitride-oxide layer sequence.
Kamiya (6,080,624) describes a non-volatile semiconductor memory with flash EEPROM memory cells. The gate dielectric, a floating-gate electrode which is provided as a storage medium, an ONO film as intermediate dielectric, a control gate electrode and a nitride film provided as a covering layer are applied to a substrate and are patterned. The source regions and the drain regions are formed by introduced diffusion. A further nitride layer is applied to the entire surface, and an electrical insulator is introduced into the spaces which are present between the webs of the gate electrodes. The insulating strips which are formed in this way run in the direction of the word lines, while the bit lines are formed by electrical conductor tracks applied to the top side.
DE 195 45 903 A1 has disclosed a read-only memory cell arrangement, in which planar MOS transistors are arranged in rows running parallel to one another. Adjacent rows alternately run along the bottom of longitudinal trenches and on webs which are present between adjacent longitudinal trenches. Accordingly, lower source/drain regions are formed on the bases of the longitudinal trenches, and upper source/drain regions are formed on the top sides of the webs which are present between the trenches. Dielectric layers are arranged on the source/drain regions as gate dielectrics, and these are supplemented, at the walls of the longitudinal trenches, by spacers comprising SiO
2
. An ONO layer sequence may be provided as the gate dielectric. The bit lines run transversely to the longitudinal trenches, and the word lines run parallel to the longitudinal trenches.
SUMMARY OF THE INVENTION
It is an object of the present invention to describe a method for fabricating a memory cell.
The memory cell according to the invention is based on the discovery that it is only possible to further reduce the dimensions of the memory cells while at the same time maintaining a sufficiently low access time for writing and reading if the bit lines have a sufficiently low resistance. For this purpose, the bit lines are formed as a result of a separate layer or layer sequence, which is patterned in strip form in accordance with the bit lines, is connected in an electrically conductive manner, in particular as a metallization, to the source/drain regions and reduces the resistance of the bit lines, being arranged on doped source/drain regions of memory transistors. This layer or layer sequence is in very general terms a layer or layer sequence which is designed in the form of strips and comprises at least one layer film which has a sufficiently low resistance for the intended purpose, irrespective of whether this layer or layer sequence is formed completely or only in a partial layer film of electrically conductive material. In the description which follows and in the claims, an electrically conductive layer or layer sequence of this type which extends at least in one layer film is in each case referred to as an electrically conductive layer. In particular, at least one material selected from the group consisting of doped polysilicon, tungsten, tungsten silicide, cobalt, cobalt silicide, titanium and titanium silicide is suitable for this purpose.
If the source/drain regions are formed from silicon, the metallization may preferably be a silicided metal layer which is fabricated using the method known as “salicide”, which represents a contraction of self-aligned silicide. In other embodiments, preferably likewise on silicon, a layer sequence, which is applied as metallization, comprising polysilicon and WSi or WN/W, as well as a covering and electrically insulating layer made from a material which is suitable for a hard mask, for example an oxide or nitride, is present on the source/drain regions of the memory transistors. The metallizations of the bit line structures are patterned directly on the substrate and, if required, partially over oxide-covered regions.
The source/drain regions of the individual memory transistors are fabricated using a high-dose source/drain implantation or by diffusion of dopant out of a suitable layer, e.g. out of polysilicon. The strip-like metallizations which are applied to the source/drain regions form the bit lines which, on account of the good conductivity of the metallizations, have a particularly low resistance. In this context, the term metallization is to be understood as meaning a metal-containing layer or a conductor track which at least has metal-like properties. The source/drain regions of the same bit line do not have to be connected to one another in an electrically conductive manner as early in the semiconductor material. Preferably, however, the bit lines are designed as buried bit lines with strip-like doped regions in the semiconductor material, which are additionally provided with the metallizations.
On the top side, which is remote from the semiconductor material, the bit line structures are preferably encapsulated in nitride layers, which are designed as strips and, in the fabrication method, serve as an etching mask for the production of channel regions of the transistors which are self-aligned with respect thereto. After a memory layer, which preferably comprises a layer sequence formed from a boundary layer, a memory layer and a further boundary layer and is formed in th

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