Method of patterning ferroelectric layers

Details Method of patterning ferroelectric layers Method of patterning ferroelectric layers

2003-02-11

2004-05-04

Hoang, Huan (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06730562

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to methods for patterning ferroelectric layers disposed on semiconductor substrates, as are used in particular for fabricating storage capacitors on large scale integrated FeRAM and DRAM components.
Ferroelectric materials are used for the fabrication of ferroelectric capacitors for applications in nonvolatile semiconductor components having a high integration density, but also for future large scale integrated volatile DRAM semiconductor memory components. The materials are able to maintain an electrical polarization in the absence of an externally applied voltage, for which reason they are used for nonvolatile semiconductor memories. At the same time, the materials also have a very high relative permittivity, for which reason they are of interest for large scale integrated DRAM memory components, for increasing the capacitance of the storage capacitors.
Preferred ferromagnetic materials for semiconductor memories are materials from the perovskite group. Representatives of the perovskite group are crystals having the compound structure ABX
3
, where A primarily denotes the ions Ca, Ba, Pb, K and rare earths, B denotes ions as Ti, Zr, Sn, Nb, Ta, etc. and X denotes an oxygen atom or a halogen atom. In memory technology, SrBi
2
Ta
2
O
9
(SBT), Pb(Zr, Ti)O
3
(PZT), or Bi
4
Ti
3
O
12
(BTO), in particular, are used as dielectrics between the plates of a capacitor. These materials have oxygen and no halogen as the third constituent, X
3
. These materials are applied to the surface and crystallized in a ferro-annealing process step in oxygen at a temperature of around approximately 800° C.
A plate material of the capacitors with a ferroelectric dielectric is preferably a noble metal that withstands the high temperatures of the ferro-annealing process step in oxygen or is converted completely or partially into a conductive oxide under these conditions. Appropriate materials for this are primarily Pt, Pd, Ir, Rh, Ru or Os or conductive noble metal oxides such as IrO
x
, RhO
x
, RuO
x
, OsO
x
, SrRuO
3
.
In general, capacitor construction in large scale integrated memory components follows the so-called stack principle, in which the capacitor contains a sandwich structure formed by a bottom electrode, a dielectric layer and a top electrode, which is applied on an insulating layer above a selection transistors.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of patterning ferroelectric layers that overcomes the disadvantages of the prior art methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a first method for patterning a ferroelectric layer on a main surface of a semiconductor substrate. The first method includes the steps of providing the semiconductor substrate having the ferroelectric layer, providing a mask for patterning the ferroelectric layer, carrying out a dry etching process using an etching gas mixture having halogen-containing gases, carrying out a heat treatment process after performing the dry etching process, and feeding H
2
O to the semiconductor substrate.
With the foregoing and other objects in view there is provided, in accordance with the invention, a second method for patterning a ferroelectric layer on a main surface of a semiconductor substrate. The second method includes the steps of providing the semiconductor substrate having the ferroelectric layer, providing a mask for patterning the ferroelectric layer, carrying out a dry etching process using an etching gas mixture having halogen-containing gases, and carrying out a heat treatment process in an O
2
-containing atmosphere after performing the dry etching process. A temperature at the semiconductor substrate is about 500° C. for about 2 to 4 hours and then is driven up to 650 to 800° C.
The methods according to the invention have the advantage that a ferroelectric layer can be patterned without the disadvantages described. Dry etching using etching gas mixtures having halogen-containing gases suppresses fence formation in the mask openings. In this case, the incorporation of halogens into the ferroelectric layer, which is harmful for the ferroelectric layer, is suppressed or reversed by the addition of H
2
O or O
2
. The feedback of oxygen into the ferroelectric material, shown using the example of H
2
O with SBT as the dielectric material, can happen e.g. through the reaction
SrBi
2
Ta
2
O
9-x
Hal
2x
+x H
2
O → SrBi
2
Ta
2
O
9
+2HHal
x
where Hal denotes F, Cl, Br and/or I.
The addition of H
2
O or O
2
results principally in the recovery of the electrostatic breakdown strength of the ferroelectric layer, which is of importance in particular when the ferroelectric serves as a dielectric of a storage capacitor and has to withstand electric fields of 5-10×10
6
V/m without a significant leakage current.
Furthermore, the adhesive strength of the ferroelectric layer, impaired as a result of the dry etching using halogen-containing etching gases, is re-established as a result of the feeding in of H
2
O and/or O
2
. The adhesive strength plays a special part e.g. if the ferroelectric layer is a dielectric between two capacitor electrode layers.
The two methods according to the invention differ in the presence and absence of H
2
O for annealing the ferroelectric layer. Whereas in the first method, the annealing of the ferroelectric layer degraded by the dry etching is affected by a reaction of H
2
O with the halogen atoms. According to the second method the annealing is effected by a reaction of O
2
with the halogen atoms. In the first method, the annealing is preferably effected in accordance with the chemical sequence:
H
2
O+2 Hal
−
→2 HHal+O
−
with Hal=F, Cl, Br, I,
whereas in accordance with the second method the annealing is preferably effected by:
O
2
+4 Hal
−
→2 Hal
2
+2 O
−
with Hal=F, Cl, Br, I.
The exchange of the halogen atoms in the ferroelectric material by the oxygen atoms in accordance with the second method is affected by heat treatment of the semiconductor substrate for 2 to 4 hours at about 500 degrees Celsius, after this time the temperature being driven up to 650 degrees to 800 degrees Celsius. The driving-up process is preferably carried out such that the semiconductor substrate is in the temperature range between 650 and 800 degrees Celsius for about 15 to 30 minutes. The atmosphere during the heat treatment preferably has a pressure of 1 atmosphere. In this case, the atmosphere preferably essentially contains oxygen. Through the heat treatment, the halogen atoms incorporated into the ferroelectric material as a result of the dry etching using the halogen-containing etching gas mixture are exchanged by the oxygen in accordance with the stoichiometric ratio. The method according to the invention furthermore has the advantage that it can be easily integrated into the overall process sequence.
The patterning of the ferroelectric layer takes place as a result of the dry etching step. The dry etching is preferably affected in plasma. The plasma contains an etching gas mixture that has halogen-containing gases and provides for a sufficient etching rate on ferroelectric layers and for a sufficient selectivity. In this case, the mask prescribes the structure of the layer to be patterned. In a preferred embodiment, the mask contains a silicon oxide or a nitride; however, it may also contain a resist which is removed again e.g. after the etching. The mask is preferably applied directly on the ferroelectric layer or on a layer which covers the ferroelectric layer.
The heat treatment step after the dry etching step is carried out in order to anneal the ferroelectric layer that has been exposed to the etching gas mixture and has thus been damaged, and to improve the adhesive strength of the ferroelectric layer with respect to the adjacent layers. The damage caused by the etching gas mixture is affected in particular a

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