Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-08-03
2004-09-21
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S698000, C257S700000, C257S737000, C257S738000, C257S778000
Reexamination Certificate
active
06794743
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes and more specifically to structure, materials and fabrication of high performance plastic ball-grid array packages designed for flip-chip assembly.
DESCRIPTION OF THE RELATED ART
Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input/output (I/O) count. BGA packages use sturdy solder balls for surface mount connection to the “outside world” (typically plastic circuit boards, PCB) rather sensitive package leads, as in Quad Flat Packs (QFP), Small Outline Packages (SOP), or Tape Carrier Packages (TCP). Some BGA advantages include ease of assembly, use of surface mount process, low failure rate in PCB attach, economic use of board area, and robustness under environmental stress. The latter used to be true only for ceramic BGA packages, but has been validated in the last few years even for plastic BGAs. From the standpoint of high quality and reliability in PCB attach, BGA packages lend themselves much more readily to a six-sigma failure rate fabrication strategy than conventional devices with leads to be soldered.
A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for improved thermal performance during device operation, necessary for consistently good electrical performance. The heat spreader is generally construed of copper and may include gold plating—representing an expensive part of the package. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
One of the substrate layers includes a signal “plane” that provides various signal lines, which can be coupled, on one end, to a corresponding chip bond pad using a wire bond (or to a contact pad using flip-chip solder connection). On the other end, the signal lines are coupled with a solder “ball” to other circuitry, generally through a PCB. These solder bails form the array referred to in a BGA. Additionally, a ground plane will generally be included on one of the substrate layers to serve as an active ground plane to improve overall device performance by lowering the inductance, providing controlled impedance, and reducing cross talk. These features become the more important the higher the BGA pin count is.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in performance characteristics such as power dissipation and the ability to maintain signal integrity in high speed operation necessary for devices such as high speed digital signal processors (DSP) and mixed signal products (MSP) Electrical performance requirements are driving the need to use multi-layer copper-laminated resin substrates (previously ceramic). As clock frequencies and current levels increase in semiconductor devices, the packaging designs are challenged to provide acceptable signal transmission and stable power and ground supplies. Providing stable power is usually achieved by using multiple planes in the package, properly coupled to one another and to the signal traces. In many devices, independent power sources are needed for core operation and for output buffer supply but with a common ground source.
As for higher speeds, flip chip assembly rather than wire bonding has been introduced. Compared to wire bonding within the same package outline, flip chip assembly offers greatly reduced IR drop to the silicon core circuits; significant reduction of power and ground inductances; moderate improvement of signal inductance; moderate difference in peak noise; and moderate reduction in pulse width degradation.
In order to satisfy all these electrical and thermal performance requirements, packages having up to eight metal layers have been introduced. The need, however, of high numbers of layers is contrary to the strong market emphasis on total semiconductor device package cost reduction. This emphasis is driving an ongoing search for simplifications in structure and materials, of course with the constraint that electrical, thermal and mechanical performances should be affected only minimally.
The complexity and cost of the BGA packages are also influenced by the number of interconnections or vias that must be fabricated in the substrate layers to provide a path to connect each of the solder balls to either the ground plane, the power planes, or desired signal lines of the signal plane. Each via requires the formation of an electrically conductive layer on the internal walls of the via, to ensure a complete electrical path. Generally, the metallization of the internal walls of each via increases the overall complexity. Consequently, multiple vias and multiple substrate layers result not only in higher BGA fabrication costs, but also lower yields.
Analyzing the total package cost shows that the cost of the substrate dominates (usually more than 50%), followed by the heat slug (usually at least 30%). In order to reduce the substrate cost, however, the number of layers should be reduced. This approach, in turn, seems to greatly endanger the electrical and thermal package performance.
An urgent need has therefore arisen to break this vicious cycle and conceive a concept for a low-cost, yet high performance BGA package structure. Preferably, this structure should be based on a fundamental design concept flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. It should not only meet high electrical and thermal performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
According to the present invention, a high-performance, high input/output ball grid array substrate is provided, which is designed for integrated circuit flip-chip assembly and has two patterned metal layers and an intermediate insulating layer.
The insulating layer has a plurality of vias filled with metal, and one of the metal layers attached to each surface. Positioned between the two metal layers, the insulating layer has a thickness and material characteristics suitable for strong electromagnetic coupling between the signal lines and the first metal layer. In this manner, a predetermined impedance to ground is provided, and cross-talk between signal lines is minimized.
The first metal layer provides the electrical ground potential and has a plurality of electrically insulated openings for outside electrical contacts.
The second metal layer has three portions: The first portion is configured as a plurality of signal lines; the second portion is configured as a plurality of first electrical power lines operable at a first potential; and the third portion is configured as a plurality of second electrical power lines operable at a second potential. The first power lines are configured so wide that their combined inductances approximate the inductance of a metal having the size of the total substrate. The second power lines are configured to serve as distributed areas having wide geometries for minimizing self-inductance and merging into a central area supporting the IC chip.
It is an aspect of the invention that the signal lines are distributed relative to the first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and close to zero effective self-inductance. Further, the signal lines are electromagnetically coupled to the ground metal such that cross-talk between signal lines is minimized.
A
Kalidas Navinchandra
Lamson Michael A.
Nguyen Dilinh
Pham Long
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