Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-13
2004-01-06
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06673682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to methods of fabricating integrated circuit devices and, more particularly, to methods of fabricating high density memory cells in integrated circuit devices.
2. Description of Related Art
Successful manufacture of high density memory devices, such as read only memory (ROM) devices, including EPROM, and EEPROM memory devices, is determined by the resolution capabilities of the processes used in the manufacture of such devices. For example, optical photolithographic processes have been developed to utilize smaller wavelengths of light to pattern the components of the semiconductor memory devices. The smaller wavelengths of light provide finer precision in exposing regions of the memory devices to the light. Currently, lasers are being employed in the processing of these memory devices.
However, as the demand for higher density memory devices increases, physical limits of the manufacturing processes are being approached. For example, in certain memory devices, the code implantation area may be about 0.15 um
2
in a 0.15 um process. The resolution limit of optical lithography can be very near 0.15 um. Thus, refraction of light may substantially affect the manufacture of memory devices, and corrective measures, such as optical proximity correction, are frequently employed to address and reduce potential manufacturing defects. These corrective processes can require a substantial amount of time and cost to implement, and thus, such corrective measures although not desirable may nonetheless be necessary in conventional methods.
In addition, as the density of the memory device elements increases, it is critical to isolate structures that will carry electrical current. The isolation structure dimensions also must be reduced to meet the density demands of the devices. One approach to isolating memory gates is to form trenches in the semiconductor substrate between the gates or the memory cells. The isolation trenches may be implanted with ions to create source and drain regions of the cells.
In order to increase the density of information that a ROM device can store, a relatively new memory architecture comprising dual bit cells is gaining acceptability. Standard ROM cell transistors are programmed (i.e., implanted) in the channel region beneath the gate to have a bit value of 1 or 0, corresponding to two states in which the cell can exist. In a two bit cell configuration, each ROM cell transistor can be programmed (i.e., implanted) on either side of the gate, with each implant corresponding to a bit. In contrast to the standard cell transistor which can be programmed to either of two states (i.e., 1 or 0), the dual bit protocol allows the cell transitor to be programmed to any of four states (i.e., 00, 01, 10, or 11). Thus, the storage capacity of each cell transistor can be increased without increasing the number of transistors on the chip.
However, as discussed above, because the densities of the components of the memory devices are approaching the physical limits of the processes used in the manufacture of the memory devices, the ion implantation process can become more difficult and time consuming. Additionally, in a dual bit process the number of implant steps may increase. Conventional methods address this problem by making smaller and smaller implantation windows to promote greater precision in the ion implantation. However, as the ion implantation window size decreases, ions are implanted over a smaller area, which can result in little, if any, implantation of the sidewalls of the isolation trenches which is necessary in the creation of certain dual bit cell architectures.
To continue to meet the demand of increasing the density of transistors and other elements of memory devices, new methods will be needed to overcome the limitations of current methods. Thus, there remains a need for methods of fabricating memory cells in integrated circuit devices which reduce or eliminate the problems associated with conventional methods, including, for example, problems associated with the physical limits of photolithographic processes.
SUMMARY OF THE INVENTION
The present invention addresses these needs by providing methods of fabricating memory devices that can improve the ion implantations of the isolation trenches in the memory devices. The invention herein disclosed provides greater control of critical dimension compared to conventional methods. The invention also provides a larger process window for ion implantation, and provides control of the trench sidewall critical dimension.
The invention disclosed herein provides methods of effectively controlling the critical dimension of the trench sidewalls to permit more effective ion implantation into the trench sidewalls, by forming a pre-code hole pattern in a semiconductor device. The pre-code hole pattern provides more effective removal of photoresist that may be present within the holes as compared to conventional methods, and creates an aperture for ion implantation into the trench sidewall that can avoid the shortcomings of conventional optical lithographic methods.
In accordance with the present invention, a method for making an integrated circuit on a semiconductor substrate may comprise the steps of (a) providing a semiconductor substrate that has a plurality of polybars disposed on the substrate and oriented parallel to each of the other polybars and disposed on either side of a trench formed in the semiconductor substrate thereby creating a channel between the polybars; (b) forming a plurality of reflective dielectric fences, formed by materials such as SOG or an oxide, between the plurality of polybars and in the trench to create a plurality of voids bounded by the plurality of polybars and the reflective dielectric fences; (c) implanting a dopant into the voids; (d) removing the reflective dielectric fences, and (e) implanting a dopant into a base of the trench. The reflective dielectric fences may be formed by removing portions of a dielectric layer (e.g. oxide) formed in the trench and channel between the polybars.
The foregoing method may also comprise the steps of adding one or more thin oxide layers to the existing structures, and adding a thin polysilicon over the thin oxide. A step of filling the voids with photoresist before implanting the dopant into the voids may be provided. A step of removing photoresist from select voids using a first photoresist mask having a pattern for a first ROM code may also be provided. A further step of the foregoing method may also include filling in the select voids with a second photoresist and removing photoresist from select voids using a second photoresist mask having a pattern for a second ROM code.
A method in accordance with the present invention may also comprise the steps of (a) providing a semiconductor substrate having a plurality of polybars disposed on the substrate, where each of the polybars are oriented parallel to the other polybars and are disposed on either side of a trench formed in the semiconductor substrate thereby creating a channel between the polybars; (b) forming a reflective dielectric fence (e.g. oxide or SOG) between the plurality of polybars to create a plurality of voids bounded by the plurality of polybars and the reflective dielectric fence; (c) filling the voids with photoresist and removing the photoresist from select voids using a first photoresist mask having a pattern for a first ROM code; (d) implanting a dopant into the voids having the photoresist removed in step (c); (e) filling the voids implanted in step (d) with photoresist and removing the photoresist from select voids using a second photoresist mask having a pattern for a second ROM code; and (f) implanting a dopant into the voids having the photoresist removed in step (e).
The above method may also further comprise the steps of adding one or more thin oxide layers and a thin polysilicon layer over the thin oxide layers. The channel between the polybars has a length and the reflective dielectric fence may be or
Macronix International Co. Ltd.
Quach T. N.
Stout, Uxa, Buyon & Mullins, LLP
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