Method of forming a semiconductor storage device

Details Method of forming a semiconductor storage device Method of forming a semiconductor storage device

2002-06-12

2004-05-11

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S637000, C438S675000

Reexamination Certificate

active

06734067

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device comprising a floating gate EEPROM (electrically erasable and programmable read-only memory) and a method of manufacturing the same.
An EPROM (erasable and programmable read-only memory) having a floating gate structure has been conventionally well known as a nonvolatile memory. In this EPROM, a floating gate electrode is disposed on a channel region sandwiched between a source region and a drain region formed in a semiconductor substrate with a gate insulating film sandwiched between the floating gate electrode and the channel region, and a control gate electrode is disposed on the floating gate electrode with an interlayer insulating film sandwiched therebetween. In a data write operation of this EPROM, hot electrons are generated in the channel region in the vicinity of the drain region in the semiconductor substrate by allowing a current to flow through the channel region under application of a high voltage between the drain region and the control gate electrode, so that a data can be written by acceleratingly injecting the hot electrons into the floating gate electrode.
On the other hand, a data erase operation of the EPROM is conventionally conducted through UV irradiation, but recently, a data erase operation by utilizing a phenomenon that electrons can tunnel through the gate insulating film formed in a small thickness has been proposed. In this data erase operation, a data is electrically erased by releasing electrons from the floating gate electrode to the source region, the drain region or the channel region, namely, toward the semiconductor substrate, by utilizing the phenomenon.
Moreover, a memory cell structure in which a data is electrically erased by using an independently formed erase electrode instead of releasing electrons toward the semiconductor substrate has recently been proposed (for example, in Japanese Laid-Open Patent Publication No. 4-340767). In this memory cell structure using the erase gate electrode, a tunneling insulating film is disposed between the erase gate electrode and the floating gate electrode, so that a data can be erased by allowing electrons to tunnel from the floating gate electrode to the erase gate electrode under application of an erase voltage to the erase gate electrode.
On the other hand, there are recently increasing demands for improvement in refinement, integration and performance of semiconductor devices, and hence, further refinement and higher performance are also earnestly required of the above-described electrically erasable floating gate EEPROM.
Now, an example of the conventional floating gate semiconductor storage device equipped with an erase gate electrode will be described with reference to FIGS.
19
and
20
(
a
) through
20
(
c
).
FIG. 19
is a plan view for showing the structure of a memory part of the conventional semiconductor storage device, and FIGS.
20
(
a
) through
20
(
c
) are sectional views thereof taken on lines XXa—XXa, XXb—XXb and XXc—XXc of FIG.
19
.
As is shown in FIGS.
19
and
20
(
a
) through
20
(
c
), the conventional semiconductor storage device includes first and second diffusion layers
102
a
and
102
b
serving as source/drain regions formed by introducing an impurity into a Si substrate
101
; an isolation insulating film
103
of a silicon oxide film deposited on the Si substrate
101
; a gate insulating film
104
of a silicon oxide film; a floating gate electrode
105
of a polysilicon film; a control gate electrode
106
of a polysilicon film; a capacitor dielectric film
107
of a silicon oxide film disposed between the floating gate electrode
105
and the control gate electrode
106
; a tunneling insulating film
111
of a thin silicon oxide film formed on the side face of the floating gate electrode
105
; an erase gate electrode
109
of a
152
polysilicon film opposing the side face of the floating gate electrode
105
with the tunneling insulating film
111
sandwiched therebetween; a gate upper insulating film
112
of a silicon oxide film formed on the control gate electrode
106
; an insulator sidewall
113
formed on the side faces of the capacitor dielectric film
107
, the control gate electrode
106
and the gate upper insulating film
112
; an interlayer insulating film
114
of a silicon oxide film deposited in a large thickness; first and second contact holes
115
a
and
115
b
formed in the interlayer insulating film
114
so as to respectively reach the first and second diffusion layers
102
a
and
102
b
; and a metal interconnect layer
116
formed so as to fill the first and second contact holes
115
a
and
115
b
and partially cover the interlayer insulating film
114
.
In this structure of the conventional semiconductor storage device, however, as the design rule is further refined to a half micron or less, in a section where the first and second contact holes
115
a
and
115
b
appear as in FIG.
20
(
c
), a distance between the first and second diffusion layers
102
a
and
102
b
serving as the source/drain regions becomes too small to easily cause a source-drain leakage. Accordingly, the lateral dimension of the first and second diffusion layers
102
a
and
102
b
shown in FIG.
20
(
b
) is also restricted. However, in order to form the first and second contact holes
115
a
and
115
b
accurately on the first and second diffusion layers
102
a
and
102
b
, it is necessary to secure an overlap margin for lithography in consideration of variation caused in the manufacturing procedures. Therefore, in order to form the first and second contact holes
115
a
and
115
b
accurately on the first and second diffusion layers
102
a
and
102
b
having a small lateral dimension in FIG.
20
(
b
), the diameter of the first and second contact holes
115
a
and
115
b
should be further reduced. In other words, the lateral dimension of the first and second contact holes
115
a
and
115
b
in the section shown in FIG.
20
(
c
) should be unavoidably reduced in order to prevent the source-drain leakage.
When the diameter of the first and second contact holes
115
a
and
115
b
is further reduced, however, the aspect ratio of the first and second contact holes
115
a
and
115
b
becomes so large that various other problems can be caused because of the structure in which the floating gate electrode
105
, the control gate electrode
106
and the erase gate electrode
109
are stacked. Specifically, a microloading phenomenon can be caused in dry etching for forming the first and second contact holes
115
a
and
115
b
, and connection failure derived from degradation of the coverage of a metal material can be caused in deposition of the metal material for forming the metal interconnect layer
116
within the first and second contact holes
115
a
and
115
b.
SUMMARY OF THE INVENTION
An object of the invention is providing a floating gate semiconductor storage device that can be refined while preventing source-drain leakage by providing means for reducing an aspect ratio of a contact hole filled in a member in contact with a diffusion layer formed in a semiconductor substrate, and a method of manufacturing the same.
The semiconductor storage device of this invention comprises a semiconductor substrate; first and second diffusion layers working as source/drain regions formed by introducing an impurity into the semiconductor substrate; an isolation insulating film formed on the semiconductor substrate in an area including a part of the first diffusion layer and a part of the second diffusion layer; a gate insulating film formed on the semiconductor substrate in an area between the first and second diffusion layers; a floating gate electrode formed on the gate insulating film; a control gate electrode formed on the floating gate electrode; a capacitor dielectric film disposed between the floating gate electrode and the control gate electrode; a tunneling insulating film formed in contact with a side face of the floating gate electrode; an erase gate electrode opposing

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