Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Reexamination Certificate
2001-06-07
2004-01-06
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
C327S198000, C327S199000, C327S022000, C327S023000
Reexamination Certificate
active
06674306
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing arbitration scheme generally and, more particularly, to an implementation for multiport arbitration using phased locking arbiters.
BACKGROUND OF THE INVENTION
Hardware devices are employed within computer systems to assist in determining the availability of computer resources (i.e., a memory chip, a hard disk drive, etc.) which can only be controlled and accessed by one requesting device at a time. However, metastable conditions can exist when contention between requests from different devices occurs. Arbitrators (or arbiters) have been designed to reduce bus contention through flags (or other such means). However, arbitrators can enter metastable states during simultaneous requests. Conventional arbitrators can therefore enter an undecided state and remain for an indefinite period of time, causing undesirable results (i.e., a system crash or hang, etc.).
Referring to
FIG. 1
, a circuit
10
is shown illustrating a conventional arbitration circuit. The circuit
10
comprises a NAND gate
12
, a NAND gate
14
and an interlock circuit
16
. The NAND gate
12
receives the signal A and an output from the NAND gate
14
. The NAND gate
14
receives a signal B and an output from the NAND gate
12
. The interlock circuit
16
presents a signal OUTA and a signal OUTB in response to the signal from the NAND gates
12
and
14
. The NAND gates
12
and
14
are implemented in a cross-coupled configuration. Therefore, the NAND gates
12
and
14
can enter a metastable condition.
Referring to
FIG. 2
, a timing diagram of the circuit
10
. is shown. The input A and the input B are shown crossing between a time T
1
and a time T
2
. The period between the time T
1
and T
2
illustrates the metastable event which can cause a push out. The circuit
10
is subject to metastability when the inputs A and B change states simultaneously.
The interlock circuit
16
attempts to resolve metastable states, but does not prevent metastable events. The arbitration circuit
10
implements cross coupled NAND arbiters (
12
and
14
) which cause delays due to metastable events. The resolution (or recovery) time of the cross coupled arbiters
12
and
14
is not predictable. While the interlock circuit
16
can try to prevent metastable states from occurring on the outputs, the interlock circuit
16
does not resolve the occurrence of the metastable events. Conventional arbitrators attempt to reduce the probability of metastable occurrences rather than eliminate such occurrences.
It is desirable to provide a method and/or architecture that provides multiport arbitration using phased locking arbiters.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.
The objects, features and advantages of the present invention include providing a method and/or architecture for detecting when a cross coupled arbiter has entered a metastable state that may (i) force each request in succession, (ii) be implemented in dual port memory applications, (iii) reduce or eliminate delays due to metastability issues, (iv) implement an interlock element to disable outputs until a metastable condition is resolved, (v) implement low voltage threshold inverters to avoid oscillation, (vi) provide a controlled arbitration time and/or (vii) arbitrate between requests for access to a memory.
REFERENCES:
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patent: 5489865 (1996-02-01), Colvin, Sr.
patent: 5638015 (1997-06-01), Gujral et al.
patent: 5754070 (1998-05-01), Baumann et al.
patent: 5789945 (1998-08-01), Cline
patent: 6072346 (2000-06-01), Ghahremani
patent: 6111436 (2000-08-01), Molnar, deceased
patent: 6184701 (2001-02-01), Kim et al.
patent: 6498513 (2002-12-01), Reynolds
patent: 6515517 (2003-02-01), Reynolds
Grahame K. Reynolds, “Metastability Recovery Circuit”, Serial No. 09/877,657, filed Jun. 7, 2001.
Grahame K. Reynolds, “Method and Apparatus for the Use of Discriminators for Priority Arbitration”, Serial No. 09/877,659, filed Jun. 7, 2001.
Grahame K. Reynolds, “Discriminator Circuit”, Serial No. 09/877,658, filed Jun. 7, 2001.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Tan Vibol
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