Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-26
2004-03-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06704897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a test system for the same directed to design for testability, and in particular, relates to an LSI test with a high-speed operation.
2. Description of the Prior Art
FIG. 8
is a block diagram of a semiconductor test device (hereinafter, referred to as LSI tester) showing a configuration on a test implementation for a semiconductor device (hereinafter, referred to as LSI). In
FIG. 8
, the reference numeral
1000
designates an LSI tester,
1001
designates a timing generator,
1002
designates a waveform formatter,
1003
designates a DC measurement unit having a power supply,
1004
designates a tester main body,
1005
designates an LSI to be tested or DUT (Device Under Test),
1006
designates a test head,
1007
designates a pin electronics,
1008
designates a test driver,
1016
designates a test comparator,
1017
designates an expected value, and
1018
designates a cable.
The LSI tester comprises the tester main body
1004
and the test head
1006
. The tester main body
1004
includes the timing generator
1001
for generating a timing signal required as an LSI test condition, the waveform formatter
1002
for determining a waveform shape, and the DC measurement unit
1003
for measuring a power supply for a device and/or DC of the device. The test head
1006
carries-out directly a signal reception/transmission to the DUT
1005
based on a control signal provided through the cable
1018
from the tester main body
1004
.
The operation will be next described below.
On testing the DUT
1005
, a test signal is generated from the tester driver
1008
of the pin electronics
1007
stored in the test head
1006
, and the test signal is applied to the DUT
1005
through pogo pins
1009
, a wiring on a DUT board
1010
, an electrode
1013
of a socket
1012
, and a wiring
1015
of an LSI package
1014
. Reversely, a reaction signal after the operation of the DUT
1005
is transmitted to the test comparator
1016
of the LSI tester
1000
through the similar route, and is compared to the expected value
1017
by the test comparator
1016
. In this manner, the LSI tester
1000
determines whether the DUT
1005
operates according to the design or not.
Since the conventional semiconductor device and test system for the same to be subjected to the LSI tester is configured as described above, though they are applied to DC, AC, function tests of LSIs, the LSI tester requires a still higher frequency and precision due to multiple pins and a higher speed test, resulting in a high price, which is not economical.
In addition, high-speed tests become difficult even in view of a physical phenomenon based on the following reasons: Waveform shapes of the test data are different from those of a real specification because of a special specification of input/output pins of the DUT, and a timing precision of the tester does not catch up with that required for the DUT.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefor an object of the present invention to provide a semiconductor device and a test system for the same to implement a self-test and a multiple pins test at the same interface specification as a real device due to an external or internal disposition of a test data generator, and to be capable of facilitating a high-speed test.
According to a first aspect of the present invention, there is provided a semiconductor device having a circuit configuration comprising: an input buffer circuit, an output buffer circuit, and an internal logic, wherein at least either a data compaction circuit having a data compaction function, a data comparison function, or both is provided at the next stage of the input buffer circuit, or a random data generation circuit is provided at the front stage of the output buffer circuit.
Here, the input buffer circuit further may comprise: a dummy driver cell including a delay circuit which generates a phase shifted clock shifted in a phase timing of a clock input to a first latch circuit and is input by the phase shifted clock, and a dummy driver circuit to be input by a data generated in such a manner that the phase shifted clock is input to the first latch circuit; and a receiver cell including a receiver circuit for receiving a data from the dummy driver cell, and a second latch circuit which latches and outputs a data from the receiver circuit and a first external pin by an input of the clock.
In addition, the output buffer further may comprise:
a dummy driver cell including a third latch circuit which latches and outputs a data from a first external pin by an input clock, and a driver circuit for receiving a data from the third latch circuit through a selector; and a dummy receiver cell including a dummy receiver circuit for receiving a data from said driver cell, a delay circuit for generating a phase shifted clock which is shifted in a phase timing, and a fourth latch circuit which latches and outputs a data from the dummy receiver circuit and the first external pin by the phase shifted clock.
According to a second aspect of the present invention, there is provided a test system for a semiconductor device comprising: a semiconductor device having a circuit configuration including an input buffer circuit, an output buffer circuit, and an internal logic, said circuit configuration being implemented by (a) a data compaction circuit having a data compaction function, a data comparison function, or both is provided at the next stage of the input. buffer circuit, or (b) a random data generation circuit is provided at the front stage of the output buffer circuit; a random data generator, incorporating the random data generation circuit, for applying a random data to an input of the input buffer circuit from the random data generation circuit; and a test board mounting the semiconductor device and the random data generator thereon, and electrically connected to each other.
Here, the semiconductor device may be circuit configured by including a selector provided between the data compaction circuit and the internal logic, and a scan path provided between the data compaction circuit and the external pin.
In addition, a clock circuit may be included in the random data generator, and a delay circuit positioned at the next stage of the clock circuit may include a D/A converter, a resistor, a capacitor, a differential amplifier, and a slew rate buffer.
Further, the random data generation circuit and the data compaction circuit may be electrically connected to each other through a plurality of latch circuits, and each of the random data generation circuit and the data compaction circuit may be constituted by inserting a logic gate in a feedback loop.
According to a third aspect of the present invention, there is provided a test system for a semiconductor device comprising: a first semiconductor device and a second semiconductor device each including (a) a data compaction circuit having a data compaction function, a data comparison function, or both provided at the next stage of an input buffer circuit, (b) a random data generation circuit provided at the front stage of an output buffer circuit, and (c) an internal logic electrically connected to the data compaction circuit and the random data generation circuit; a first socket assigned for a tester by all the pins of the first semiconductor device; a second socket assigned for the tester by only the pins selected for a self-test of the second semiconductor device; a test board on which the first and second semiconductor devices are mounted through the first and second sockets, respectively, wherein an output pin and an input pin of the second semiconductor device are electrically connected to each other on the test board.
REFERENCES:
patent: 5619512 (1997-04-01), Kawashima et al.
patent: 5701309 (1997-12-01), Gearhardt et al.
patent: 6105156 (2000-08-01), Yamauchi
patent: 6112321 (2000-08-01), Shimada et al.
patent: 6114866 (2000-09-01), Matsuo e
De'cady Albert
Dooley Matthew C.
Mitsubishi Denki & Kabushiki Kaisha
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