Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-30
2004-05-04
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S233000, C438S238000, C438S279000, C438S586000, C438S587000, C438S638000, C438S649000
Reexamination Certificate
active
06730553
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to semiconductor structures. More particularly, it pertains to making semiconductor devices so these devices operate at high speed while having high density.
BACKGROUND OF THE INVENTION
In the making of certain semiconductor devices, modern semiconductor processes may require a p-type semiconductor material to be adjoined to an n-type semiconductor material, but not for the purpose of forming a diode. However, a diode is naturally formed when a p-type semiconductor material is adjoined to an n-type semiconductor material. This situation allows current to undesirably flow if the diode is activated by accident in certain areas of a semiconductor structure. This current may render a semiconductor device defective. One solution to this problem is to place a conductive material on top of the n-type semiconductor material and the p-type semiconductor material as illustrated in
FIGS. 1A and 1B
.
FIG. 1A
is a cross-sectional view taken from the front of a conventional semiconductor structure
10
and
FIG. 1B
is a cross-sectional plan view of the conventional semiconductor structure
10
. The semiconductor structure
10
includes a gate oxide layer
8
that overlies an n-channel active area
2
, a field region
18
, and a p-channel active area
20
. The n-channel active area
2
includes a p-type well
22
containing highly doped n-type areas
4
, as shown in FIG.
1
B. These highly doped areas
4
form a drain region and a source region of an n-channel transistor. The highly doped n-type areas
4
are doped with donor impurities. The p-channel active area
20
includes an n-type well
24
containing highly doped p-type areas
4
, as shown in FIG.
1
B. The highly doped p-type areas
4
are doped with acceptor impurities, and these highly doped p-type areas
4
form a drain region and a source region of a p-channel transistor.
The n-channel active area
2
also includes an n-type polycrystalline silicon strip
10
A forming a transistor gate for the n-channel transistor, and the p-channel active area
20
includes a p-type polycrystalline silicon strip
10
B forming a transistor gate for the p-channel transistor. A gate cap
12
, which is formed from a nonconductive material, overlies both the n-type polycrystalline silicon strip
10
A and the p-type polycrystalline silicon strip
10
A. A spacer
14
surrounds a portion of the semiconductor structure
10
as shown in FIG.
1
B. Both the spacer
14
and the gate cap
12
electrically isolate and structurally support the transistor gates from other conductive layers (not shown) in the semiconductor structure
10
.
In complementary semiconductor structures, such as CMOS, dual-doped polycrystalline silicon is used to simultaneously form p-channel and n-channel devices. Particularly, an SRAM cell uses a single polycrystalline line to form a gate electrode for both the pull-up device and the pull-down device. This single polycrystalline line is dual-doped with both acceptor impurities and donor impurities shown as portions
10
A, B in FIG.
1
A.
The n-type polycrystalline silicon strip
10
A abuts against the p-type polycrystalline silicon strip
10
B. As explained hereinbefore, a diode may undesirably form from the semiconductor/semiconductor contact of the n-type polycrystalline silicon strip
10
A and the p-type polycrystalline silicon strip
10
B. However, for CMOS SRAM cells ohmic contact (i.e., semiconductor/metal contact) is desired. Should a voltage of an appropriate magnitude and polarity be accidentally placed between the n-type polycrystalline silicon strip
10
A and the p-type polycrystalline silicon strip
10
B, current may undesirably flow.
One solution is to use a salicide process to strap a conductive stack
13
on top of the n-type polycrystalline silicon strip
10
A and the p-type polycrystalline silicon strip
10
B. This conductive stack
13
shorts the two types of polycrystalline silicon strips
10
A, B so they are at the same potential. Therefore, undesirable current cannot flow, so the net current between the two types of polycrystalline silicon strips
10
A, B is zero. The conductive stack
13
comprises a tungsten layer
9
that overlies a tungsten nitride layer
11
. Other conductive (stack) materials, such as tungsten silicide or cobalt silicide, are also used.
One of the problems with this approach is that the conductive stack
13
may promote cross-diffusion. Cross-diffusion occurs when impurities from one type of polycrystalline silicon diffuse up to the conductive stack
13
and diffuse down to the other type of polycrystalline silicon. This movement of impurities undesirably transforms the designed semiconductor characteristic of the polycrystalline silicon. Another problem is that certain conductive materials may decompose during processing, which forms an undesired nonconductive layer that may degrade performance of a semiconductor device. For example, the tungsten layer
9
must be used with the tungsten nitride layer
11
, but the tungsten nitride layer
11
may react with either of the polycrystalline silicon strips
10
A, B to form silicon nitride, which is a nonconductive compound. This nonconductive compound may increase the vertical resistance of the gate stack
15
, and thereby, may degrade the speed at which a semiconductor device that includes the gate stack
15
can operate. To avoid this increase in the vertical resistance, some semiconductor manufacturers have supplanted the use of the tungsten layer
9
and the tungsten nitride layer
11
with a layer of cobalt silicide, tungsten silicide, or titanium silicide, but in so doing, one problem is replaced with another problem. The cobalt silicide may increase the horizontal resistance of the gate stack
15
compared to the tungsten layer
9
, and once again, the operational speed of the semiconductor device using the gate stack
15
may be degraded.
If the operational speed of the semiconductor devices is degraded, the operational speed of circuits that are built from these semiconductor devices may be degraded as well. However, certain circuits often need to quickly process signals, such as timing, address, and data. Without the means to solve the problems discussed above, the operational speed of these semiconductor devices may be less than desired, which may lead to their eventual lack of acceptance in the marketplace. Thus, there is a need for structures and methods to enhance semiconductor structures to inhibit cross-diffusion and decrease vertical and horizontal resistance so that semiconductor devices, which are built upon these semiconductor structures, may operate at high speed.
SUMMARY OF THE INVENTION
One illustrative aspect includes a method for strapping a gate structure of a transistor in a periphery area of a semiconductor structure. The method includes forming from a nonconductive stack a trench that superjacently abuts along a substantially length of a dual-doped polycrystalline silicon line having a p-type strip abutting an n-type strip. The nonconductive stack includes a stopping layer that stops an etching process once etched away to define the bottom of the trench. The method further includes filling the trench with a conductive substance to strap the dual-doped polycrystalline silicon line. The trench has a large cross-sectional area to decrease a horizontal resistance of the transistor so as to increase the performance of the transistor.
REFERENCES:
patent: 5899742 (1999-05-01), Sun
patent: 6069038 (2000-05-01), Hashimoto et al.
patent: 6083828 (2000-07-01), Lin et al.
patent: 6274409 (2001-08-01), Choi
patent: 6300178 (2001-10-01), Sunouchi
Cho Chih-Chen
Wang Zhongze
Dorsey & Whitney LLP
Thomas Toniae M.
Zarabian Amir
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