Integrated circuit memory devices having efficient multi-row...

Details Integrated circuit memory devices having efficient multi-row... Integrated circuit memory devices having efficient multi-row...

2003-03-19

2004-05-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S221000, C365S189080, C365S196000, C365S200000, C365S225700, C365S230060, C365S239000, C365S203000

Reexamination Certificate

active

06741512

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and, more particularly, to semiconductor memory devices that utilize spare memory cells to replace normal memory cells that are defective.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) devices typically comprise large arrays of memory cells. A semiconductor memory device is frequently treated as defective if one or more memory cells does not operate properly. As the integration density and the processing rate of semiconductor memory devices increase, the probability of occurrence of a defective cell increases. Accordingly, the yield of a wafer, which determines the manufacturing cost of DRAMs and is represented by the ratio of the number of non-defective chips to the total number of chips manufactured on a single wafer, may decrease. To improve the yield of a wafer for memory devices having a high integration density, methods for correcting defective cells become increasingly important.
To correct defective cells, redundancy technology has been used. Conventional redundancy technology uses a spare (i.e., redundant) memory cell block located near a normal memory cell block.
FIG. 1
is a partial block diagram illustrating a conventional semiconductor memory device in which defective cells within a normal memory cell block are replaced using a spare memory cell block. Referring to
FIG. 1
, a semiconductor memory device
100
includes a memory cell block
110
having a plurality of memory cells in rows and columns. The memory cell block
110
is divided into a normal memory cell block NCB and a spare memory cell block SCB. The semiconductor memory device
100
also includes a normal word line driver
120
for driving a word line connected to cells within the normal memory cell block NCB and a spare word line driver
130
for driving a word line connected to cells within the spare memory cell block SCB.
The normal word line driver
120
is illustrated in FIG.
2
. The normal word line driver
120
includes a precharger
210
, a selector
220
, a normal word line driver enabler
230
and a driver
240
. PMOS transistors
211
and
212
are turned on in response to activation of a precharge signal PREB to a logic “low” level so that nodes A and B are precharged to the level of a power supply voltage VCC. The precharge signal PREB is activated to a logic “low” level before a word line driving operation is performed. The logic “high” levels of the nodes A and B pass through the respective inverters of the normal word line driver
240
and then become logic “low” levels at normal word lines NWE
0
and NWE
1
. When the normal word lines NWE
0
and NWE
1
are held at the logic “low” level, the rows of memory cells that are connected to NEW
0
and NEW
1
within the normal memory cell block NCB are inactive.
When a normal word line enable signal FB is activated to a logic “high” level, an NMOS transistor
231
in the normal word line driver enabler
230
is turned on and the normal word line driver
120
is enabled. NMOS transistors
221
and
222
within the selector
220
are selectively turned on in response to internal address signals DRAiB and DRAi. The internal address signals DRAiB and DRAi may be generated by an address decoder (not shown) using conventional techniques. When the internal address signal DRAiB is at a logic “high” level, the NMOS transistor
221
in the selector
220
is turned on. When this occurs, the signal at node A transitions from a logic “high” level to a logic “low” level. The logic “low” level at node A causes the inverter within the driver
240
to drive the normal word line NWE
0
to a logic “high” level. The normal word line NWE
0
at the logic “high” level selects a row of memory cells MC
0
within the normal memory cell block NCB of FIG.
1
. The timing chart of this operation is illustrated in FIG.
3
.
Referring again to
FIG. 1
, when a selected memory cell MC
0
in the normal memory cell block NCB is defective, the memory cell MC
0
is replaced by a spare memory cell SC
0
in the spare memory cell block SCB. As will be understood by those skilled in the art, the occurrence of a defective memory cell within a normal row of memory cells typically causes the entire row to be replaced by a spare row. To achieve this replacement, operation, the semiconductor memory device
100
is provided with a spare word line driver
130
for selecting a row of spare memory cells SC
0
. The spare word line driver
130
is shown in FIG.
4
.
Referring to
FIG. 4
, the spare word line driver
130
includes a precharger
410
, a selector
420
, a spare word line enabler
430
and a driver
440
. The spare word line driver
130
also includes a spare word line driver enable signal line precharger
450
and a programmable decoder
460
. A PMOS transistor
451
in the spare word line driver enable signal precharger
450
is turned on in response to activation of the precharger signal PREB to a logic “low” level. This causes a first spare word line driver enable signal F to become a logic “high” level. Here, fuses F
1
and F
2
within the programmable decoder
460
may be selectively cut when a defective cell within the normal memory cell block NCB has been identified. For example, when the memory cell selected by the internal address signal DRAiB in the normal memory cell block NCB is defective, the fuse F
1
in the programmable decoder
460
is cut. Therefore, since the fuse F
1
is cut, the spare word line driver enable signal F does not become a logic “low” level even if the NMOS transistor
461
is turned on in response to the logic “high” level of the internal address signal DRAiB.
Thereafter, when a second spare word line driver enable signal PRAD is activated to a logic “high” level, an NMOS transistor
431
in the spare word line driver enabler
430
is turned on. When this occurs, node C is pulled to a logic “low” level through the NMOS transistor
421
(turned on in response to an enable signal F having a “high” logic level) and the NMOS transistor
431
. The logic “low” level at the node C passes through the inverter within the driver
440
and thus becomes a logic “high” level at a spare word line SWE. The spare word line SWE at the logic “high” level selects the spare memory cell SC
0
in the spare memory cell block SCB. The row of spare memory cells can replace the row of defective memory cells MC
0
in the normal memory cell block NCB.
The operation of such a semiconductor memory device
100
can be verified by testing for defective cells. To reduce test time, a multi row address test method in which a plurality of word lines are sequentially driven and tested in response to a single command has been proposed. However, this test method typically has the following problems which will be described with reference to FIG.
5
. For purposes of illustration herein, it is assumed that an internal address used for addressing a defective cell within a normal memory cell block is DRAiB. When an internal address DRAi addressing a non-defective cell is input to a semiconductor memory device during a multi-row address test, a normal word line NWE is enabled, and the first spare word line driver enable signal F transitions from a logic “high” level to a logic “low” level. This transition of the enable signal F to a logic “low” level occurs because the NMOS transistor
462
in the decoder
460
of
FIG. 4
is turned on in response to the address signal DRAi. Thereafter, the first spare word line driver enable signal F should become a logic “high” level and turn on the selector
420
when the internal address DRAiB addressing a defective cell is input. However, the first spare word line driver enable signal F is maintained at the logic “low” level after the address signal DRAi is applied. Accordingly, a spare word line SWE is not enabled when the internal address DRAiB is applied. This limitation associated with the circuit of
FIG. 4
reduces the effectiveness of the test method whereby the normal word line NWE and the spare word line SWE are sequentially enabled during

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