Semiconductor device having increased metal silicide...

Details Semiconductor device having increased metal silicide... Semiconductor device having increased metal silicide...

2002-07-31

2004-01-06

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S655000

Reexamination Certificate

active

06673665

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a semiconductor device having metal silicide portions formed therein and a method of forming metal silicide portions on silicon-containing regions.
2. Description of the Related Art
Field effect transistors represent the most frequently used circuit elements in modern integrated circuits. Typically, a huge number of field effect transistors is simultaneously formed on an appropriate substrate and are connected to establish the required functionality of the circuit. In presently available integrated circuits, silicon is the primarily used semiconductor material and forms an essential part of a field effect transistor. Generally, a silicon-based field effect transistor comprises two highly doped silicon regions, also referred to as drain and source regions, that are embedded in a lightly and inversely doped silicon region, the so-called n-well or p-well, depending on the type of transistor. The drain and the source regions are spaced apart with a channel region interposed, wherein a conductive channel forms between the drain and source regions in the channel region upon application of an appropriate voltage to a gate electrode that is usually formed over the channel region and is separated therefrom by a gate insulation layer, often provided as a gate oxide layer.
Thus, in the most common field effect transistors, the gate structure essentially comprises the gate electrode formed above the gate insulation layer, with polysilicon often being selected as the material for forming the gate electrode for several reasons. For instance, polysilicon exhibits high compatibility with subsequent high temperature processes. Moreover, the polysilicon interface with thermal silicon dioxide (SiO
2
) is well understood and electrically stable. Furthermore, polysilicon is more reliable than aluminum gate materials and can be deposited conformally over steep topography.
However, problems arise when polysilicon is used as a gate material, due to its higher resistivity compared to aluminum. In fact, the defects in the grain boundaries of the polysilicon, together with the decreased overall free carrier concentration, cause the resistivity of polysilicon lines, such as the gate electrode, to increase.
In particular, even when doped at the highest practical concentration, a 0.5&mgr; thick polysilicon film has a sheet resistance of about 20 &OHgr;/sq (compared to 0.05 &OHgr;/sq for a 0.5&mgr; thick aluminum film). The resulting high values of interconnect line resistance can lead to relatively long RC time constants (i.e., long propagation delays) and severe DC voltage variations within a VLSI (very large scale integration) circuit.
To overcome this drawback, several solutions have been proposed and developed in the art. Among these solutions, the formation of metal silicides on the top of the polysilicon gate structure proved to be the most reliable one for obtaining the lowest resistance values.
A typical prior art method of forming metal silicides on silicon-containing regions, such as the gate electrode, of a CMOS transistor will be described in the following with reference to
FIGS. 1
a
-
1
d.
In
FIGS. 1
a
-
1
d,
reference
1
relates to an arbitrary section of a substrate, for instance a silicon wafer, on which a CMOS transistor
100
is to be formed. In particular, in
FIG. 1
a,
there is depicted the situation at the moment during the manufacturing process when metal silicides are to be formed. Accordingly, in
FIG. 1
a,
reference
2
relates to isolation structures which have been previously formed. These isolation structures
2
divide the section of the substrate
1
into two portions, on which the PMOS transistor and the NMOS transistor are to be formed, respectively. In this particular case, the PMOS portion is depicted on the left side of the figure and the NMOS portion on the right side of the figure.
Moreover, in
FIGS. 1
a
-
1
d,
references
3
p
and
3
n
relate to the gate polysilicon electrodes of the PMOS and NMOS transistors, respectively. References
4
p
and
4
n
relate to oxide side spacers formed on the sidewalls of the gate polysilicon electrodes. References
6
p
and
6
n
relate to the gate insulation layers on the PMOS region and the NMOS region, respectively. Finally, references
5
p
and
5
n
relate to the source and drain regions of the PMOS and NMOS transistors, respectively.
Subsequently, in a next step, a metal layer
7
is deposited on the CMOS region
100
, as depicted in
FIG. 1
b.
Usually, either titanium (Ti) or cobalt (Co) is used as a metal for forming the metal layer
7
, and, typically, a physical vapor deposition (PVD) sputtering process is carried out for depositing the metal layer
7
.
Once the metal layer
7
has been deposited, a low temperature thermal step (approximately 450° C. or 650° C. for cobalt and titanium, respectively) is carried out to react the metal in contact with silicon (Si) on the source/drain regions
5
p
and
5
n
and the polysilicon gate electrodes
3
p
and
3
n.
During the thermal step, inter-diffusion of the polysilicon and metal occurs, on the upper surface
10
p,
10
n
of the polysilicon gate electrode
3
p
and
3
n
as well as on the source/drain regions
5
p
and
5
n
not covered by oxide. As a result, metal silicides
8
p
and
8
n
are formed, as depicted in
FIG. 1
c,
whereby the metal is at least partially consumed.
In a subsequent step, as depicted in
FIG. 1
d,
the unreacted metal is selectively removed with a selective wet-etch step, leaving behind the metal silicide layers
8
p
and
8
n
on top of the polysilicon gate electrodes
3
p
and
3
n
and on the source and drain regions
5
p
and
5
n.
Commonly, a further heat treatment is carried out at a higher temperature than the previous heat treatment to transform the metal silicide
8
p,
8
n
into a more stable phase that exhibits a lower resistance than the metal silicide formed during the previous low temperature heat treatment. For example, if cobalt is used in the first heat treatment, a cobalt monosilicide is formed, which is then converted into a cobalt disilicide.
Since the finally-obtained metal silicide layers
8
p
and
8
n
exhibit a sheet resistance which is much lower compared to the sheet resistance of polysilicon, the total resistance of the gate electrodes
3
p,
3
n
including the metal silicide layers
8
p,
8
n
is decreased.
The prior art method described above has accomplished satisfactory results for devices having minimum feature sizes of 0.5&mgr; and more. The above method, however, is not completely adequate to compensate for the increase of the polysilicon sheet resistance which arises in cases of deep-sub-micron devices, i.e., with feature sizes smaller or equal to 0.25&mgr;. The reason for this can be explained as follows. As a general rule, decreasing the transistor size, i.e., the channel length, in
FIG. 1
the horizontal distance between the drain/source regions
5
p
or between the drain/source region
5
n,
requires reducing the thickness of the gate insulation layer
6
p,
6
n
and necessitates shallower source/drain regions, which in turn restricts the achievable thickness of the metal silicides
8
p,
8
n.
As the metal silicides
8
p,
8
n
for the gate electrodes
3
p,
3
n
are simultaneously formed with the metal silicides of the drain and source regions, the thickness, and thus the reduction in resistance, of the gate silicide is also restricted.
As the cross-sectional dimensions of the polysilicon gate electrodes decrease as a result of the continuous miniaturization of the devices, the sheet resistance of the polysilicon portions of the gate structures inversely increases and becomes predominant with respect to the low resistance of the silicide layers. The final, total resistance of the gate electrodes is therefore only scarcely influenced by the silicide layer but practically corresponds to the resistance of the polysilicon portion of the gate

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