High voltage transistors with graded extension

Details High voltage transistors with graded extension High voltage transistors with graded extension

2002-02-28

2004-01-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S228000, C438S289000, C257S408000

Reexamination Certificate

active

06677210

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to systems and methods for creating high voltage Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). More specifically, this invention relates to systems and methods of creating high voltage MOSFETs with graded extensions that provide a high breakdown voltage.
High voltages applied to the terminals of a MOSFET can cause breakdown in the transistor as a result of the high electric fields generated.
FIG. 1A
illustrates a cross section of a first prior art high voltage lateral DMOS transistor
100
. Transistor
100
includes source
123
, body
116
, drain
113
, and n-epitaxial layer
117
. A disadvantage of transistor
100
is that it typically has a high threshold voltage (e.g., 1.5-5 volts) that is not compatible with low voltage (LV) CMOS technology.
FIG. 1B
illustrates a cross section of a second prior art high voltage lateral DMOS transistor
130
. Transistor
130
includes source
123
, body
136
, drain
113
, and diffused n-type drain extension region
137
.
FIG. 1C
illustrates a cross section of a third prior art high voltage lateral DMOS transistor
160
. Transistor
160
includes source
123
, body
116
, drain
113
, n-epitaxial layer
167
, and N+ buried layer
169
.
Transistors
100
,
130
and
160
each include thick field oxide
111
and thin oxide
114
. Thick field oxide
111
reduces the electric field on the drain side of gate
115
. Thick field oxide
111
in transistors
100
,
130
, and
160
includes bird's beak encroachment
121
. A disadvantage of transistors
100
,
130
, and
160
is that bird's beak
121
increases the ON-resistance R
DS(ON)
of transistor
100
.
Transistors
100
,
130
, and
160
have a large overlap of the gate polysilicon over the drain extension region that results in an increase in the gate-to-drain capacitance. This overlap is a further disadvantage of the prior art, because it reduces the frequency response of the transistor.
For lateral DMOS
160
to have a drain source breakdown voltage BV
dss
greater than 100 volts, N-epitaxial layer
167
must be greater than 10 microns, which is not compatible with low voltage (LV) CMOS or LV BICMOS processes. DMOS
160
also has a high output capacitance, because all of N-epitaxial layer
167
is coupled to the output of the transistor, which negatively affects the propagation delay and switching characteristics of the device.
Lateral DMOS transistors
100
,
130
, and
160
limit potential high breakdown voltages, because they use drain extensions with non optimized doping gradients. When doping is substantially constant throughout a transistor's drain between the gate and the N+ drain contact, the charge concentration of majority carriers is not optimized. Electric fields present in the drain region next to the gate are the same as the electric fields present in drain region next to the N+ drain contact region, increasing the possibility of breakdown at very high electric fields.
BRIEF SUMMARY OF THE INVENTION
High voltage transistors of the present invention have a gradient of majority charge carriers in the drain that increases laterally farther away from the gate. By varying the lateral charge concentration in the drain, potentially severe electric fields may be controlled and manipulated.
To increase the drain breakdown voltage of a transistor, severe electric fields in the drain can be moved farther from the transistor's channel and gate regions. This may be accomplished by providing graded drain extensions with a charge carrier profile that increases laterally away from the channel region. The breakdown voltage in a transistor of the present invention may approach the theoretical limit of the device. The graded drain extensions reduce the electric fields near the transistor's channel region and other hot, electron-sensitive, areas.
A laterally increasing charge carrier profile in the drain may, for example, be formed by diffusing one or more drain dopants into multiple overlapping wells. The charge carriers in the overlapping wells compensate the drain dopant to produce the laterally increasing charge carrier profile.
High voltage transistors of the present invention may have a variety of geometric configurations. For example, transistors of the present invention may include overlapping regions that form a triple drain extension. High voltage transistors of the present invention may be, for example, MOS field effect transistors including P-channel and N-channel MOSFETs.
As another example, the present invention includes transistors with a ring-gate structure that eliminates the risk of premature edge (termination) breakdown and increases device performance and reliability. Transistors of the present invention may also have a striped-gate structure that can be realized with a single metal layer. Minimizing the number of metal layers can reduce production costs, increase wafer device density, and reduce routing problems.
Fabrication of high voltage transistors of the present invention may result in low output capacitance, a lower gate-to-drain capacitance, a low threshold voltage of (e.g., 0.7V), and a low drain-source ON resistance R
DS(ON)
. A low drain-source ON resistance can reduce the voltage drop across a transistor's channel, thus increasing performance and reliability. Furthermore, a transistors of the present invention may be compatible with both low voltage CMOS and low voltage BiCMOS fabrication processes.


REFERENCES:
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patent: 5346835 (1994-09-01), Malhi et al.
patent: 5424226 (1995-06-01), Vo et al.
patent: 5438220 (1995-08-01), Nakagawa et al.
patent: 5646054 (1997-07-01), Rhee
patent: 04-208571 (1992-07-01), None
Gilles Thomas et al., “High-Voltage Technology Offers New Solutions for Interface Integrated Circuits”, IEEE Transactions on Electron Devices, vol. ED-33, No. 12, Dec. 1986.
Monir El-Diwany et al., “1.5&mgr;m Analog BiCMOS/DMOS Process for Medium Voltage and Current Power ICs Applications up to 50V”, Proceedings of the 1995 Bipolar/BiCMOS Circuits and Technology Meeting.
Claudio Contiero et al., “Characteristics and Applications of a 0.6&mgr;m Bipolar-CMOS-DMOS Technology combining VLSI Non-Volatile Memories”, IEEE, 1996.
Chin-Yu Tsai et al., “16-60V Rated LDMOS Show Advanced Performance in an 0.72&mgr;m Evolution BiCMOS Power Technology”, IEEE, 1997.

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