Method of forming shallow trench

Details Method of forming shallow trench Method of forming shallow trench

2002-04-05

2003-02-04

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S391000

Reexamination Certificate

active

06514817

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a method of forming a shallow trench, and more particularly, to a method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate.
BACKGROUND OF THE INVENTION
All the while, manufacturers expect to achieve a larger capacitance and a higher element accumulation degree in a limited space of a DRAM cell. Accordingly, the construction of a deep trench capacitor and the construction of a STI (i.e., Shallow Trench Isolation) are simultaneously implemented in the processes of manufacturing a DRAM cell.
Please refer to FIGS.
1
(
a
),
1
(
b
) and
1
(
c
) and FIGS.
2
(
a
),
2
(
b
) and
2
(
c
). They show conventional procedures of etching a shallow trench on a semiconductor substrate
10
which has deep trench capacitors construction
11
. Because the depth of the collar structure
112
of the deep trench capacitor construction
11
can not be controlled to keep constant in the manufacturing process, as shown in FIG.
1
(
a
) and FIG.
2
(
a
), the variation of the depth of the collar structure occurs, so that the depth is either too shallow or too deep. For covering the range of the variation of the depth, people use borosilicate glass (BSG)
131
, silicon nitride (SiN)
132
, and silicon oxide (SiO
2
)
133
to construct the mask
13
so as to perform an etching process with respect to the polycrystalline silicon
111
and portions of the substrate
10
with a constant depth under a high selectivity ratio (silicon relative to silicon oxide). Accordingly, the shallow trench construction is formed as shown in FIG.
1
(
b
) and FIG.
2
(
b
). They clearly show that the bottom of the shallow trench construction is not flat because the collar structure
112
constituted by the silicon oxide which is remained after the etching process of high selectivity ratio. According to the conventional procedures, we need one more additional etching process of high selectivity ratio (silicon oxide relative to silicon) in order to eliminate the phenomenon that the portion of the collar structure
112
constituted by the silicon oxide is projected from the bottom. However, as shown in FIGS.
1
(
c
),
2
(
c
), they have clearly shown that the bottom of the shallow trench construction is still not flat. Some portions
113
project from the bottom, and some portions
114
are recessed at the bottom. As a result, in the consequent manufacturing process, the occurrence of defect increases such that the yield is affected thereby. Therefore, the present applicant tried to rectify this drawback by this invention.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a shallow trench which can reduce the occurrence of defect and increase the yield rate by means of flattening the bottom of the shallow trench.
According to the present invention, a method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate is disclosed, each deep trench capacitor construction having a collar construction and a conductor construction. The method of forming a shallow trench comprises steps of (a) defining a mask by forming a mask layer on the semiconductor substrate which has the deep trench capacitor constructions, (b) performing a first etching process with respect to the regions which is not covered by the mask so as to form a first depth trench, wherein the first etching process has a relatively high selectivity ratio of the conductor construction relative to the mask, and (c) performing a second etching process with respect to the first depth trench so as to form a second depth trench, wherein the second etching process has a selectivity ratio of the conductor construction relative to the collar construction substantially close to 1.
Preferably, the semiconductor substrate is a silicon substrate.
Preferably, the collar construction is constructed by silicon oxide.
Preferably, the conductor construction is constructed by polycrystalline silicon.
Preferably, the mask layer includes a silicon oxide layer formed on the semiconductor substrate, a silicon nitride layer formed on the silicon oxide layer, and a doped silicon oxide layer formed on the silicon nitride layer.
Preferably, the doped silicon oxide layer is a borosilicate glass (BSG) layer.
Preferably, the first etching process has a relatively high selectivity ratio of silicon relative to silicon oxide.
Preferably, the reacting gases of the first etching process comprises hydrogen bromide (HBr), chlorine (Cl
2
), oxygen (O
2
), and inert gas.
Preferably, wherein the second etching process has a selectivity ratio of the polycrystalline silicon relative to the silicon oxide substantially close to 1.
Preferably, the second etching process is a plasma etching process.
Preferably, the reacting gases of the plasma etching process comprises trifluoromethane (CHF
3
), tetrafluoromethane (CF
4
), and chlorine (Cl
2
).
Preferably, the depth of the bottom of the first depth trench is less then that of the top of the collar construction.


REFERENCES:
patent: 5358891 (1994-10-01), Tsang et al.
patent: 6037210 (2000-03-01), Leas
patent: 6074909 (2000-06-01), Guening
patent: 6140673 (2000-10-01), Kohyama
patent: 6172390 (2001-01-01), Rupp et al.
patent: 6255683 (2001-07-01), Radens et al.
patent: 6391706 (2002-05-01), Wu et al.
patent: 6451648 (2002-09-01), Gruening et al.
patent: 019903597 (2000-10-01), None
patent: 000969514 (2000-05-01), None

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