Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-24
2003-11-18
Picardat, Kevin (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S637000, C438S652000, C257S750000, C257S758000
Reexamination Certificate
active
06649509
ABSTRACT:
RELATED PATENT APPLICATION
This application is related to Ser. No. 10/004,027 Oct. 24, 2001, assigned to a common assignee.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a post passivation scheme that provides low-resistance metal interconnects in addition to bond pads on the surface of an Integrated Circuit device that is covered with a conventional layer of passivation.
(2) Description of the Prior Art
Improvements in semiconductor device performance are typically obtained by scaling down geometric dimensions of the Integrated Circuit (IC) devices, resulting in decreasing the cost per device while improving device performance. Metal connections, which connect the Integrated Circuit to other circuit or system components, become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on device performance. Parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce metal interconnect resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, one approach has been is to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation. This approach however limits the interconnect network to fine-line interconnects, which is associated with low parasitic capacitance and high line resistance. The latter two parameters, because of their relatively high values, degrade device performance, an effect which becomes even more severe for high-frequency applications and for long interconnect lines that are, for instance, typically used for clock distribution lines. Also, fine-line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.
It has previously been stated that it is of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistance. The invention provides such a method. An analogy can be drawn in this respect, as follows: the currently used fine-line interconnection schemes, which are created under a layer of passivation, are the streets in a city. In the post-passivation interconnection scheme of the present invention, the interconnections that are created above a layer of passivation can be considered the freeways between cities.
Due to the current trend in the creation of IC devices, the interconnection metal lines become thinner and the operating voltages that are applied to the devices become lower. For current sub-micron devices, with interconnect lines having a cross-section of about 0.18 &mgr;m, the voltage that is applied to the internal circuits is typically about 2.0 Volts or less. For such low voltage supplies, the IR voltage drop that is introduced by the interconnect lines has a relatively large impact on device functionality and performance, this in particular for circuits within a device that are removed by a considerably distance from bond pads. Most seriously affected are circuits that are located in the center of a device with wirebonding pads located at the periphery of a chip, for those devices the IR drop that is introduced by interconnect lines can cause either device malfunction or a degradation in the operational speed of the device. The invention addresses these concerns.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a low impedance metal interconnect system with bond pads on top of a Integrated Circuit device that is covered with a conventional layer of passivation.
Another objective of the invention is to provide a scheme for metal interconnects with bond pads that negates the effects of IR voltage drops introduced by the interconnect wires for applications where a voltage supply of 2 Volts or less is used.
Yet another objective of the invention is to provide a low-cost, high-performance post passivation metal interconnection system with bond pads that allows interconnection of power, ground, signal and clock lines over long distances.
A still further objective of the invention is to provide a low-cost, high-performance post passivation metal interconnection system that allows interconnection of power, ground, signal and clock lines to relatively far removed bond pads without introducing significant IR voltage drop introduced by the metal interconnect system.
In accordance with the objectives of the invention a new post-passivation metal interconnect scheme is provided over the surface of an IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. The post passivation metal scheme is connected to external circuits through wirebonding pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding. The composite metal is created by a bulk (low-resistance) conduction metal covered by a layer of (wire-bondable) metal to which wire bond connections can be readily made. A diffusion metal may be applied between the bulk metal and the wire-bondable metal, in addition a layer of Barrier-Metal (BM) may be required underneath the bulk conduction metal.
REFERENCES:
patent: 5701666 (1997-12-01), DeHaven et al.
patent: 6168974 (2001-01-01), Chang et al.
patent: 6180426 (2001-01-01), Lin
patent: 6303423 (2001-10-01), Lin
patent: 6306749 (2001-10-01), Lin
Huang Ching-Cheng
Lee Jin-Yuan
Lei Ming-Ta
Lin Mou-Shiung
Ackerman Stephen B.
Megic Corporation
Picardat Kevin
Saile George O.
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