Method of forming smaller trench line width using a spacer...

Details Method of forming smaller trench line width using a spacer... Method of forming smaller trench line width using a spacer...

2001-04-02

2003-12-16

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S700000, C438S702000, C438S952000

Reexamination Certificate

active

06664180

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of forming the trench line width using a spacer hard mask.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to put millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation (such as light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the coating through a photomask or reticle causes the image area to become selectively crosslinked and consequently either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble (i.e., uncrosslinked) or deprotected areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. As feature sizes are driven smaller and smaller, optical systems are approaching their limits caused by the wavelengths of the optical radiation.
One alternative to projection lithography is EUV lithography. EUV lithography reduces feature size of circuit elements by lithographically imaging them with radiation of a shorter wavelength. “Long” or “soft” x-rays (a.k.a, extreme ultraviolet (EUV)), wavelength range of lambda =50 to 700 angstroms are used in an effort to achieve smaller desired feature sizes.
In EUV lithography, EUV radiation can be projected onto a resonant-reflective reticle. The resonant-reflective reticle reflects a substantial portion of the EUV radiation which carries an IC pattern formed on the reticle to an all resonant-reflective imaging system (e.g., series of high precision mirrors). A demagnified image of the reticle pattern is projected onto a resist coated wafer. The entire reticle pattern is exposed onto the wafer by synchronously scanning the mask and the wafer (i.e., a step-and-scan exposure).
Although EUV lithography provides substantial advantages with respect to achieving high resolution patterning, errors may still result from the EUV lithography process. For instance, the reflective reticle employed in the EUV lithographic process is not completely reflective and consequently will absorb some of the EUV radiation. The absorbed EUV radiation results in heating of the reticle. As the reticle increases in temperature, mechanical distortion of the reticle may result due to thermal expansion of the reticle.
Both conventional projection and EUV lithographic processes are limited in their ability to print small features, such as, contacts, trenches, polysilicon lines or gate structures. As such, the critical dimensions of IC device features, and, thus, IC devices, are limited in how small they can be.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need to form smaller feature sizes, such as, smaller trench lines. Yet further, there is a need to form the trench line width using a spacer hard mask.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of forming trench lines. This method can include providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.
Briefly, another exemplary embodiment is related to a method of manufacturing an integrated circuit. This method can include patterning mask features on an anti-reflective coating (ARC) layer where the mask features are separated by a first distance defined as a first critical dimension; transferring the patterned mask features to the ARC layer to form ARC features; depositing a layer of spacer material over the ARC features; etching the layer of spacer material to form spacers on lateral sides of the ARC features where the spacers and ARC features define re-structured ARC features; and etching trench lines using restructured ARC features as a hard mask. The re-structured ARC features are separated by a second distance defined as a second critical dimension. The second critical dimension is less than the first critical dimension.
Briefly, another embodiment is related to an integrated circuit having trench lines. This integrated circuit is manufactured by a method that can include providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.


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