Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-27
2003-11-18
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S267000
Reexamination Certificate
active
06649473
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method of fabricating a nonvolatile semiconductor memory device. More particularly, it relates to a method of fabricating a floating gate for a split gate flash memory.
2. Related Art of the Invention
Complementary metal-oxide semiconductors (CMOS's) can be classified in two major categories, random access memory (RAM) and read only memory (ROM). Random access memory is a volatile memory from which the stored data disappears when powered off. In contrast, the data stored in a read only memory is not affected when powered off. In the past few years, the market occupancy of the read only memories has gradually increased, of which the expansion of flash memory is most significant. The electrical programmable function allows a single memory cell of the flash memory to be written to. In addition, the flash memory can also be electrically erased block-by-block, wherein each block comprises multiple memory cells. Application flexibility and convenience are superior to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and programmable read only memory. More importantly, the fabrication cost of flash memory is low. Due to the above advantages, flash memories have been broadly applied to electronic products such as digital cameras, digital camcorders, cellular phones, portable computers, personal stereos, and personal digital assistants (PDA). More and more products use flash memory for data and information storage. To accommodate portability, electronic products are increasingly smaller, but with more varied and powerful functionality. Data processing and storage capacities are thus larger. Capacity of flash memories has thus increased from about 4 MB to about 256 MB. Flash memory of about 1 GB capacity is foreseeable. In the conventional fabrication process of the split gate flash memory, including the most crucial process to form the floating gate, the application of a photomask is inevitable. A conventional process to form a floating gate of a memory cell of a split gate flash memory is introduced as follows.
In
FIG. 1A
, a thermal oxidation process is performed on a P-type substrate
100
. For example, the local oxidation process (LOCOS) is performed to form a field oxide layer (not shown) to define an active region. A first insulating layer
110
is formed on the active region of the substrate
100
. A chemical vapor deposition (CVD) process is performed to deposit a doped polysilicon layer on the first insulating layer
110
, so that a first conductive layer
115
is formed. A silicon nitride layer is formed on the first conductive layer
115
as a masking layer
120
. The masking layer is used as a hard mask in the subsequent process.
Referring to
FIG. 1B
, a part of the masking layer
120
is removed to form an opening
125
which exposes the surface of the first conductive layer
115
.
Referring to
FIG. 1C
, an oxidation process is formed to a floating gate oxide layer
130
on the exposed first conductive layer
115
.
In
FIG. 1D
, an isotropic etching process is performed to remove the masking layer
120
. Anisotropic etching is performed using the floating gate oxide layer
130
as a hard mask, so that the remaining first conductive layer
115
and the first insulating layer
110
uncovered by the floating gate oxide layer
130
are removed successively to leave the portions underlying the floating gate oxide layer
130
. As a result, the surface of the substrate
110
is exposed. The remaining first conductive layer
115
serves as the floating gate
136
, while the remaining first insulating layer
110
serves as the gate insulating layer
112
. The poly tip
138
is formed for the floating gate
130
to perform spike discharge during the erase operation of the flash memory. The floating gate of the conventional split gate flash memory is thus completed.
In the conventional fabrication as above, the hard mask defines an opening. The surface of the conductive layer exposed in the opening is then oxidized to form the floating gate oxide layer. Anisotropic etching technique is then applied to remove the doped polysilicon conductive layer uncovered by the floating gate oxide layer. The floating gate is thus formed on the remaining doped polysilicon conductive layer underlying the floating gate oxide layer. However, to comply with the high integration demand, the dimensions of all devices have to be reduced. The conventional fabrication process that uses the hard mask to remove the uncovered polysilicon layer to form the poly tip results in the sharpness of the poly tip being insufficient when device dimensions are reduced. As a result, function and performance of the split gate flash memory are impacted.
SUMMARY OF THE INVENTION
In the present invention, a masking layer with an opening is formed on the conductive layer, followed by a process for filling the opening with a material with low oxygen diffusion coefficient. In the subsequent oxidation process, the barrier of such material with low oxygen diffusion coefficient allows differential oxidation rate in the opening. Oxidation rate of the conductive layer is faster near the upper portion of the opening. With the remaining conductive layer on the lower sidewall and bottom surface of the opening, a sharper poly tip is formed. The poly tip, the remaining conductive layer on the bottom surface and lower sidewall of the opening, and the underlying conductive layer construct the floating gate. Such process is adapted in the present invention to form a split gate floating gate. The process adapted in the present invention is more easily controlled than conventional fabrication. Moreover, the poly tip formed by the present invention is sharper.
A method for fabricating a floating gate of a flash memory cell is provided by the present invention. The fabrication method comprises the following steps. A semiconductor substrate is provided. An active region is defined in the surface of the semiconductor substrate. A first insulating layer is formed in the active region on the substrate. A first conductive layer is formed on the first insulating layer, and a masking layer is formed on the first conductive layer. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer and fills the first opening. A thermal oxidation process is performed to oxidize the surface of the second conductive layer in contact with the second insulating layer, such that a third insulating layer is formed between second conductive layer and insulating layer. Because oxygen diffuses slowly in the second insulating layer, oxidation of the second conductive layer is faster near the upper portion of the first opening. As the conductive layer on the bottom surface and lower sidewall of the first opening are not fully oxidized, a poly tip is formed on the second conductive layer at the corner of the first opening, that is, at the joint of the lower sidewall and the bottom surface of the first opening. The second and third insulating layers are then removed to form a second opening, so that the remaining second conductive layer and the poly tip are exposed. A fourth insulating layer fills in the second opening as a floating gate insulating layer. The masking layer and the first conductive layer underlying the masking layer are then removed. Thus, a floating gate is formed by the remaining second and first conductive layers.
REFERENCES:
patent: 5972752 (1999-10-01), Hong
patent: 6180461 (2001-01-01), Ogura
patent: 6482700 (2002-11-01), Chen et al.
patent: 6511881 (2003-01-01), Lin
patent: 6562673 (2003-05-01), Lin
Huang Chung-Lin
Lin Chi-Hui
Nanya Technology Corporation
Picardat Kevin M.
Quintero Nelson A.
LandOfFree
Method of fabricating a floating gate for split gate flash... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a floating gate for split gate flash..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a floating gate for split gate flash... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3175196