Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-21
2003-12-09
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S593000, C438S303000, C438S305000
Reexamination Certificate
active
06660585
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memories and in particular flash memory cells.
2. Description of Related Art
One of the problems associated with a flash memory is bit line and word line disturbs which are caused by bit line and word line voltages being coupled to the deselected cells as well as the selected cells on the same bit line or word line during erase, program and read operations. The effect of the bit line and word line disturb is to change the threshold voltage of the disturbed cells. This is an accumulative effect that over time will cause a memory error, will shorten the program and erase cycles, and reduce product life.
In U.S. Pat. No. 5,880,991 (Hsu et al.) is described an integration of a flash EEPROM with a DRAM and an SRAM on the same chip. The process to form the floating gate incorporates the process for making a stacked capacitor for the DRAM. In U.S. Pat. No. 5,654,917 (Ogura et al.) a process is described for fabricating a flash memory array. The embedded structure of the flash memory cells are used in a Domino and Skippy Domino schemes to program and read the cells. In U.S. Pat. No. 5,479,036 (Hong et al.) a structure and process is described for a split gate flash memory cell. The process utilizes self aligned techniques to produce an array of flash memory cells. In U.S. Pat. No. 5,172,200 (Muragishi et al.) an EEPROM flash memory cell is described which utilizes a lightly doped drain structure for both the drain and the source. An insulating layer with a protruding “visor like” shape is used to improve the resistance of the insulating layer to destruction caused by high electric fields. In U.S. Pat. No. 5,168,465 (Harari) a split channel and other cell configurations are used to produce an EEPROM. The elements of the EEPROM are produced using a cooperative process of manufacture to provide self alignment. A programming technique allows each memory cell to store more than one bit of information.
Bit line and wordline disturb conditions occur in memory arrays that use stacked gate cells. This can occur during programming and reading when a combination of voltages must be applied to a particular stacked gate cell but also extend to other cells that are deselected. A disturb condition also occurs during erasure of a column of cells where word lines for the cells in the column are at a high negative potential and extend to other cells in other columns that are deselected and inhibited for erasure. Although a particular operation (read, program or erase) are not carried out in the other cells that are inhibited, the bias on a bit line or a word line extends to the other cells that are inhibited and can reduce the charge on the floating gates of those cells, albeit at a slow rate. The charge on the floating gate of a stacked gate cell determines the threshold voltage which determines the logical value of the stored data in the cell. The charge can be reduced over time from repeated disturb operations until the threshold voltage of the stacked gate drops below a point where the stored value is in error.
SUMMARY OF THE INVENTION
In this invention a stacked gate flash memory cell and its usage is described to produce reduced disturb conditions. A control gate is stacked on top of a floating gate separated by an insulator such as an oxide. A lightly doped drain is implanted on the drain side of the stacked gates and a heavily doped source is implanted on the source side of the stacked gates. Sidewalls are formed on the sides of the stacked gates, and after the sidewalls are formed a heavily doped drain is implanted into the semiconductor substrate. The heavily doped drain forms a contact region with the lightly doped drain which was implanted previous to the forming of the sidewalls.
The source in the present invention is used to both program the flash memory cell by means of hot electrons and to erase the memory cell by using Fowler-Nordheim tunneling. The lightly doped drain (LDD) greatly reduces the electric field at the drain, reducing the hot electron generation and as a result reducing bit line disturbs during programming. Other techniques, such as double diffused drain and large angle tilted implanted drain, can be used to produce the effects of the LDD to reduce the electric field and reduce the hot electron generation at the drain. Depending upon product requirements such as increased breakdown and reduced band to band tunneling a double diffused source can be used in place of a heavily doped arsenic source.
During an erase operation the present stacked gate flash memory cell is biased similar to prior art with the selected bit lines connected to the drain either floating or connected to zero volts while the source through the selected source line is connected to +5V and the control gate connected to the selected wordline is biased to −9V. Unselected wordlines connected to gates of unselected cells are biased to 0V during an erase operation.
During programming of the present flash memory cell, a selected wordline connected to a number of gates is biased to +9V while the selected source line is connected to +5V. The selected source line applies the +5V bias to the gates connected to the selected wordline as well as gates connected to wordlines that are not selected. The drain of the transistor of the cell that is being programmed is biased to 0V through a selected bit line. Unselected bit lines connected to drains of cells not being programmed are pre-biased to Vcc and then biased to +5V to minimize the effects of a transient soft program disturb. The transient soft program disturb occurs in cells connected to both selected wordlines at +9V and selected source lines at +5V. When an unselected bit line is raised to +5V a transient current can flow through the cell which causes a disturb condition. To minimize this effect the unselected bit lines are pre-charged to Vcc which reduces the bit line charging voltage (+5V−Vcc). The +5V bias on unselected bit lines will cause a bit line disturb in cell connected to unselected wordlines. This disturb condition is minimized by the design of the drain that is lightly doped at the drain side of the channel which greatly reduces hot electron generation.
During a read the gate of the memory cell being read is connected to Vcc through a word line, the source is connected to 0V through the source line and the drain is connected to +1.5V through a bit line. A soft read disturb is not a concern because of the LDD structure and the higher drain voltage can be used compared to +1V in prior art.
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Chan Vei-Han
Chen Hung-Sheng
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B
Aplus Flash Technology Inc.
Meier Stephen D.
Saile George O.
Thomas Toniae M.
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