Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-29
2003-10-28
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06638813
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to eliminate polysilicon residual material located between buried stack capacitor and other elements of a static random access memory (SRAM) cell.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, have allowed the performance of memory cells comprised with sub-micron devices to be improved, while still resulting in a reduction of the fabrication cost for the specific semiconductor chip comprised with sub-micron devices. The use of sub-micron features allow performance degrading parasitic junction capacitances to be reduced. In addition the use of sub-micron features also allow a greater number of smaller semiconductor chips to be obtained from a specific size starting substrate, thus reducing the cost of a specific semiconductor chip. The semiconductor chips comprised with devices formed with sub-micron features, still provide device densities equal to, or greater than counterpart semiconductor chips comprised with devices formed with larger features. To further decrease the size of semiconductor chips specific designs for such cells such as SRAMs, have to considered. SRAM designs comprised with six devices, four N channel, metal oxide semiconductor field effect transistors (MOSFET) devices, and two P channel MOSFET devices, limit the ability to reduce semiconductor chip size, therefore new SRAM cell designs such as a pseudo SRAM or a one transistor SRAM (1T SRAM), have been used to minimize semiconductor chip size.
The use of pseudo or 1T SRAM designs entail the use of only a capacitor structure along with only a MOSFET device, to satisfy the requirements of these new SRAM cell designs. To further minimize cell area a buried stack capacitor structure, formed in a shallow trench isolation (STI) region, is used to satisfy the capacitance requirements of the pseudo or 1T SRAM cells. The buried stack capacitor structure provides the needed cell capacitance without consuming the additional semiconductor area, or process complexity encountered with counterpart capacitor structures such as stacked capacitor, or trench capacitance structures. However is imperative during the fabrication of pseudo or 1T SRAM cells, to eliminate leakage or shorting paths between the buried capacitor structure and an adjacent MOSFET device such as a pass gate transistor. The fabrication of the polysilicon gate structure of the MOSFET device, accomplished after completion of the buried stack capacitor structure, can result in residual polysilicon, or polysilicon stringers located between these elements. The process conditions encountered by the STI region, used to accommodate the buried stack capacitor structure, can result in surface topographies which can prove to be conducive to formation of undesirable polysilicon residuals or stringers.
This invention will describe a novel process sequence allowing a composite spacer to be formed on the sides of a buried stack capacitor structure, which in turn allow a smoother, final STI surface to result, thus reducing the risk of polysilicon residuals or stringers forming during the subsequent definition of a MOSFET polysilicon gate structure. Prior art such as Kirlin et al, in U.S. Pat. No. 5,976,928, as well as Quek et al, in U.S. Pat . No. 5,744,853, describe processes for forming capacitor structures for memory cells, however these prior arts do not employ the unique process sequence described in this present invention in which a composite insulator layer is formed on the sides of a completed buried stack capacitor structure prior to definition of a gate structure of an adjacent MOSFET device, resulting in STI topographies less conducive to allowing formation of overlying polysilicon residual or stringers than counterparts formed without the composite spacer.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a pseudo SRAM or a 1T SRAM cell, comprised with a buried stack capacitor structure formed in shallow trench isolation (STI) region, and comprised with an adjacent MOSFET device.
It is another object of fabricate the MOSFET device of the SRAM cell after formation of the buried stack capacitor structure.
It is still another object of this invention to form a composite insulator spacer on the sides of the buried stack capacitor structure, prior to formation of a polysilicon gate structure of the adjacent MOSFET device.
It is still yet another object of this invention to subject the composite insulator spacer to a wet etch procedure to obtain a smooth top surface topography comprised of the partially etched composite spacer and the wet etch treated STI region, allowing subsequent definition of the MOSFET polysilicon gate structure to be accomplished without leaving polysilicon residuals or stringers on the surface located between the MOSFET and buried capacitor elements.
In accordance with the present invention a process for forming a smooth surface topography, and a gradual slope, between a buried stack capacitor structure located in and on an STI region, and an adjacent MOSFET device, via formation of, and wet etch treatment of a composite insulator spacer formed on the sides of a completed buried stack capacitor structure prior to formation of a MOSFET gate structure, is described. After formation of an STI region in a top portion of a semiconductor substrate, storage node structures are formed in recesses in the STI region. Completion of the buried stack capacitor structure comprising formation of a capacitor dielectric layer, and of an overlying capacitor top plate, results in a first portion of the non-recessed STI region now covered by the capacitor top plate, while a second portion of the non-recessed STI region remains uncovered. A composite insulator spacer comprised of an underlying silicon nitride component and an overlying silicon oxide component, is defined on the sides of the completed buried stack capacitor structure. The silicon oxide component of the composite insulator spacer is obtained via an anisotropic dry etch procedure followed by a wet etch procedure, with the wet etch procedure resulting in the final definition of the silicon oxide spacer as well presenting a gradual slope at the interface between the composite insulator spacer and the partially etched STI region. Subsequent formation of a gate structure for a MOSFET device located adjacent to the buried stack capacitor structure, is accomplished without polysilicon residual or stringer formation on the underlying smooth surface topography, or on the gradual slope presented by the underlying insulator material located between the buried stack capacitor structure and the adjacent MOSFET device.
REFERENCES:
patent: 5744853 (1998-04-01), Quek et al.
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 5999474 (1999-12-01), Leung et al.
patent: 6028804 (2000-02-01), Leung
Chang Chung-Wei
Chen Wen-Cheng
Chiang Wen-Chuan
Huang Kuo-Ching
Tzeng Kuo-Chyuan
Pert Evan
Taiwan Semiconductor Manufacturing Company
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