Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-10
2003-12-02
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000, C438S596000
Reexamination Certificate
active
06656794
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a memory area and a logic circuit area. More specifically the invention pertains to a method of manufacturing a semiconductor device, on which each of non-volatile memory devices formed in the memory area has two charge accumulation regions relative to one word gate.
2. Description of the Related Art
One type of non-volatile semiconductor memory devices is MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon), in which a gate insulating layer between a channel area and a control gate is a multi-layered body of a silicon oxide layer and a silicon nitride layer and charges are trapped by the nitride silicon layer.
FIG. 22
shows a known MONOS non-volatile semiconductor memory device (refer to: Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers p. 122-123).
Each MONOS memory cell
100
has a word gate
14
, which is formed on a semiconductor substrate
10
via a first gate insulating layer
12
. A first control gate
20
and a second control gate
30
are formed as side walls on both sides of the word gate
14
. A second gate insulating layer
22
is present between the bottom of the first control gate
20
and the semiconductor substrate
10
. An insulating layer
24
is present between the side face of the first control gate
20
and the word gate
14
. Similarly the second gate insulating layer
22
is present between the bottom of the second control gate
30
and the semiconductor substrate
10
. The insulating layer
24
is present between the side wall of the second control gate
30
and the word gate
14
. Impurity layers
16
and
18
, each of which constitutes either a source area or a drain area, are formed in the semiconductor substrate
10
to be located between the control gate
20
and the control gate
30
of adjoining memory cells.
Each memory cell
100
accordingly has two MONOS memory elements on the side faces of the word gate
14
. These two MONOS memory elements are controlled independently. Namely each memory cell
100
is capable of storing 2-bit information.
A memory area including such MONOS memory cells and a logic circuit area including peripheral circuits of memories are formed on an identical semiconductor substrate in a semiconductor device. A prior art method of manufacturing such a semiconductor device first forms memory cells in the memory area and subsequently forms peripheral circuits in the logic circuit area. The manufacturing method forms diverse wiring layers via an insulating layer, after formation of the memory area and the logic circuit area.
The manufacturing method forms an insulating layer of, for example, silicon oxide, and polishes the insulating layer by CMP (chemical mechanical polishing) technique. The polishing is carried out until exposure of stopper layers under the insulating layer in the memory area.
The polishing rate of the insulating layer is, however, not constant but is varied, and the insulating layer in the logic circuit area is polished relatively faster than the insulating layer in the memory area. There is accordingly a possibility that gate electrodes in the logic circuit area are exposed, prior to exposure of the stopper layers in the memory area.
Exposure of the gate electrodes in the logic circuit area may cause resulting MOS transistors in the logic circuit area to be exposed to an etching gas, which affects the properties of the MOS transistors, in a subsequent process of patterning word gates of memory cells.
OF THE INVENTION
The object of the present invention is thus to provide a manufacturing method of a semiconductor device, which effectively prevents exposure of gate electrodes in a logic circuit area in an insulating layer polishing process.
In order to attain at least part of the above and the other related objects, the present invention is directed to a method of manufacturing a semiconductor device, which includes a memory area having a non-volatile memory device and a logic circuit area including a peripheral circuit of the non-volatile memory device. The manufacturing method includes the steps of (a) providing a semiconductor substrate, which includes a semiconductor layer, a first insulating layer formed on the semiconductor layer, a first conductive layer formed on the first insulating layer, and a stopper layer formed on the first conductive layer; (b) patterning the stopper layer and the first conductive layer in the memory area; (c) forming control gates as side walls on both side faces of the patterned first conductive layer via an oxide nitride oxide (ONO) membrane in the memory area; (d) etching out the stopper layer in the logic circuit area; (e) patterning the first conductive layer in the logic circuit area to form a gate electrode of an insulated gate field effect transistor; (f) forming a second insulating layer in both the memory area and the logic circuit area; and (g) polishing the second insulating layer to expose the stopper layer in the memory area. The step (d) performs over-etching to remove an upper portion of the first conductive layer, simultaneously with removal of the stopper layer.
The manufacturing method of the invention performs over-etching to remove an upper portion of the first conductive layer in the logic circuit area, simultaneously with etching out the stopper layer. The method subsequently patterns the first conductive layer to form the gate electrode in the logic circuit area. The height of the gate electrode is lowered, because of the removed upper portion of the first conductive layer.
In the manufacturing method of the invention, the height of the gate electrode formed in the logic circuit area is lowered. In the subsequent process of polishing the second insulating layer, even when the polishing rate of the second insulating layer is not constant but varied and the second insulating layer in the logic circuit area is polished relatively faster than the second insulating layer in the memory area, this arrangement of the invention effectively prevents exposure of the gate electrode in the logic circuit area, prior to exposure of the stopper layer in the memory area.
In one preferable application of the manufacturing method of the invention, the step (c) includes the sub-steps of: (c−1) forming the ONO membrane in at least the memory area; (c−2) forming a second conductive layer on the ONO membrane; and (c−3) etching the second conductive layer to form the control gates of the second conductive layer via the ONO membrane on both side faces of the patterned first conductive layer in the memory area.
These sub-steps enable the control gates to be formed as side walls via the ONO membrane on both side face of the patterned first conductive layer.
In one preferable embodiment of the manufacturing method of the semiconductor device according to the present invention, the step (g) applies CMP technique to polish the second insulating layer.
This technique is suitable for leveling off the inter-layer insulating layer over the whole surface of the semiconductor substrate.
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Yutaka Hayashi et al.; “Twin MONOS Cell with Dual Control Gates”; 2000, IEEE VLSI Technology Digest of Technical Papers; 2000.
Kuo-Tung Chang et al. “A New Sonos Memory Using Source-Side Injection for Programming”;IEEE Electron Device Letters, Vol 19, No. 7, Jul. 1998 pp 253-255.
Wei-Ming Chen et al., A Novel Flash Memory D
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