Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-05-11
2003-12-02
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C326S046000
Reexamination Certificate
active
06658617
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to built-in self-testing of logic (“LBIST”), and more particularly, to an apparatus and a method for handling 1-hot multiplexers during LBIST in an integrated circuit environment.
2. Description of Background Art
For high performance circuit designs, it is common to have outputs from a decoder, e.g., 2-to-4 decoder, feeding state elements, e.g., latches or flip-flops, which then feed select lines of the passgate multiplexers. For circuit designs that employ scans, the state elements are typically scannable.
During general system operation this configuration is acceptable because the system operates according to rules that ensure that the select lines of the passgate multiplexers are always orthogonal, i.e., only one of them is on. However, under test conditions, e.g., during a built-in self-testing of logic (“LBIST”), the scannable state elements get random data that no longer abides by the orthogonal rule. The LBIST process is a signature-based methodology that depends on deterministic results. At any given time during an LBIST test, the test responses must be known and are compressed into a structure that, based on a predefined polynomial, will produce a unique signature. This special structure is a multiple-input shift register (“MISR”).
With regard to LBIST, a consequence of having either no select line in an on state or having multiple select lines in an on state causes a number of problems. For example, when no select line is in an on state, i.e., a 0-hot condition, the multiplexer will be floating. This results in a high current state that is detrimental to the reliability of the integrated circuit. If multiple select lines are in an on state, this will cause a problem with regard to contention of a node driven by a drive voltage, VDD, and ground. This will also result in a condition that is detrimental to the reliability of the integrated circuit. Thus, although each condition described would allow for safe operation of the system during system operation, the consequence of each condition during LBIST would be destruction of the validity of the LBIST results.
Therefore, there is a need for an apparatus and a method that allows for ensuring a 1-hot condition for a multiplexer during a built-in self-testing of logic in an integrated circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided an apparatus for obtaining valid values during a built-in self-testing of logic (“LBIST”). The apparatus includes a first multiplexer, a second multiplexer, and a 1-hot init circuit. The 1-hot init circuit includes a third multiplexer, a forth multiplexer, a scan register, a first inverter and a second inverter.
Each of the first, second, third, and fourth multiplexers include three inputs and an output. The first input of the first multiplexer and the first input of the second multiplexer are coupled to receive data signals from, for example, a pseudo-random pattern generator (“PRPG”) for bits. The output of the first multiplexer is coupled to an input of the 1-hot init circuit. The output of the 1-hot init circuit is coupled to the second input of the second multiplexer and the second input of the first multiplexer. The output of the second multiplexer is coupled to a signature compression circuit, for example, a multiple input shift register.
Within the 1-hot init circuit, the scan register is coupled to the output of the first multiplexer to receive its output signal. The scan register includes state elements, for example logic flip flops, that receive data signals from a decoder. Each state element may have two inputs and two outputs. An output of a next to last state element is coupled with the first inverter and to a second input of the third multiplexer. The output of the first inverter is coupled to the first input of the third multiplexer.
The output of the third multiplexer is coupled to an input of a last state element. An output of this last state element is coupled to the second input of the fourth multiplexer and an input of the second inverter. The output of the second inverter is coupled to the first input of the fourth multiplexer. The output of the fourth multiplexer is coupled to the second input of the second multiplexer.
For a proper 1-hot initialization, when an input signal (or 1-hot initialization signal) is asserted high (or logical 1 or supply voltage, VDD) a signal is inverted when going through the last two elements of the scan register, the first inverter, the third multiplexer, the second inverter, and the fourth multiplexer within the 1-hot init circuit. This becomes an input for the third multiplexer. Under a flush condition (i.e., the scan clocks to the state elements of the scan register are both asserted and scan in input is held to a logical zero (or ground)) all but the last state element in the scan register will be flushed to zero while the last state element receives a value of one due to the inversion by the second inverter. This causes the output signal from the fourth multiplexer to be a logical zero. Thus, the scan register receives a 1-hot value (e.g., a “0001” with four state elements in the scan register) after a flush. This ensures that the values a 1-hot multiplexer selects are orthogonal and the output from the second multiplexer is valid.
It is noted that the first and the second multiplexers provide a means to allow 1-hot initialization during flush. It may also ensure 1-hot values in the scan register during LBIST by allowing a 1-hot value to re-circulate between the output of the first multiplexer, the output of the 1-hot init circuit, and back to the input of the scan register of the 1-hot init circuit.
The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.
REFERENCES:
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5625303 (1997-04-01), Jamshidi
patent: 5875346 (1999-02-01), Luick
patent: 5955912 (1999-09-01), Ko
patent: 5991909 (1999-11-01), Rajski et al.
patent: 6199184 (2001-03-01), Sim
patent: 6219811 (2001-04-01), Gruetzner et al.
patent: 6327687 (2001-12-01), Rajski et al.
patent: 6380724 (2002-04-01), Mahurin et al.
patent: 6380780 (2002-04-01), Aitken et al.
patent: 6452423 (2002-09-01), Das et al.
Nachman, L.; Saluja K.K.; Upadyaya, S.; Reuse, R.; Random pattern testing for sequential circuits revisited; Proceedings of Annual Symposium on Fault Tolerant Computing, Jun. 25-27, 1996.
Lin, C.-J.; Zorian Y.; Bhawmik, S.; PSBIST: A partial-scan based built in self-test scheme; Proceedings International Test Conference; Oct. 17-21, 1993, pp. 507-516.
Fenwick & West LLP
Fujitsu Limited
Tu Christine T.
LandOfFree
Handling a 1-hot multiplexer during built-in self-testing of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Handling a 1-hot multiplexer during built-in self-testing of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Handling a 1-hot multiplexer during built-in self-testing of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168161