Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2003-03-06
2003-12-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S185090, C365S189070, C365S200000
Reexamination Certificate
active
06661712
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device in which a volatile memory, such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), and an electrically rewritable or reprogrammable nonvolatile memory, such as a flash memory, are packaged together with a control processing unit, such as a central processing unit, over a semiconductor substrate, and, more particularly, the invention relates to a repair technique which is effective when applied to an on-chip type large-scale integrated circuit, such as a DRAM-consolidated LSI (Large-Scale Integration), a DRAM-embedded LSI or a system LSI.
Nowadays, the large scale of a semiconductor integrated circuit device is in the category of a system on-chip, such as a DRAM-consolidated LSI, a DRAM-embedded LSI or a system LSI.
As a semiconductor integrated circuit device is provided with a larger scale, its internal defects can be less ignored. Especially, a memory, such as a DRAM, a SRAM or a flash memory, is expected to have a relatively small area, but a large storage capacity, so that it becomes susceptible to defects caused by the remarkably fine working during manufacture and the resultant miniaturization of signals. Therefore, the application of a redundancy circuit technique to such semiconductor circuit devices is important so that an expected system operation can be achieved irrespective of the occurrence of more or less defects
For enlarging the scale of a semiconductor integrated circuit device, it is frequently desirable to apply a trimming technique for achieving the desired circuit characteristics. By this trimming technique, an analog amount, such as an internal voltage or current, and a quasi-analog amount, such as the timing of a timing signal, can be sufficiently brought to a desired value irrespective of the manufacturing dispersion of the semiconductor integrated circuit device.
The redundancy circuit technique and the trimming technique for a large-scale semiconductor integrated circuit device are well-known. One such technique is disclosed in Japanese Patent Laid-Open No. 334999/1995, and in corresponding U.S. Pat. No. 5,561,627, of Hitachi, Ltd., and is used in a program for providing defect repair information using the memory cells of an electrically reprogrammable nonvolatile memory, such as a flash memory. In this technique, repair information specifying a defective memory cell in the nonvolatile memory is stored in the memory cell of the nonvolatile memory, the repair information is latched in an internal latch circuit at the time of initialization; and the latched repair information and an access address are compared so that the access is replaced, in the case of coincidence, by the access to a redundant memory cell.
On the other hand, another technique is disclosed in Japanese Patent Laid-Open No. 214496/1998, and in corresponding U.S. patent application Ser. No. 09/016300, of Hitachi, Ltd., and in which trimming information is stored for use in the storage region of a portion of a nonvolatile memory, such as a flash memory. In accordance with this technique, more specifically, there is provided a trimming circuit for finely adjusting the output clamp voltage of voltage clamp means for providing an operating power source for the flash memory so that the trimming information for determining the state of the timing circuit is programmed in the memory cells of the flash memory. The programmed trimming information is read out in a reset operation from the flash memory and is internally transferred to a register. The state of the trimming circuit is determined by using the transferred trimming information. As a result, the clamp voltage to be outputted from voltage clamp means is trimmed to a value suitable for the operation of the flash memory, thereby compensating for the manufacturing dispersion of the semiconductor integrated circuit device.
An example of a system LSI is described on pp. 34 to 38 of “Electronic Materials” (issued in January, 1998, by Kabushiki Gaisha Kogyo Chosakai), wherein, as seen in
FIG. 4
thereof, a volatile memory, such as a flash memory, and a DRAM are consolidated together with a CPU (Central Processing Unit). The technique for forming the nonvolatile memory and the DRAM by a common process is already described in U.S. Pat. No. 5,057,448. On the other hand, examples of a semiconductor integrated circuit device packaging a flash memory and a DRAM together with a CPU on one semiconductor substrate are described in Japanese Patent Laid-Open Nos. 52293/1989 and 124381/1998.
SUMMARY OF THE INVENTION
Our preceding patent application has proposed the use of storage elements of one flash memory for repairing a defect or to effect trimming within a closed range of the flash memory. In view of the large-scale integration represented by a system on-chip, we have investigated the efficient use of a nonvolatile memory, or one circuit module packaged in the large-scale integrated circuit device in relation to another circuit module. In the course of this investigation, we have considered the utilization of the stored information of the nonvolatile memory to repair a defect of a volatile memory, other than the nonvolatile memory itself. we have recognized the following new problems in the investigation of such repair of a volatile memory.
In order to provide the nonvolatile memory with the required repair information, more specifically, a procedure is needed to reflect the repair information on the volatile memory. This reflection of the information desirably should be realized at a high speed, even if the amount of repair information increases, to cope with an increase in the defects in accordance with the construction of the volatile memory or the provision of a large storage capacity.
In studies subsequent to that investigation, Japanese Patent Laid-Open No. 131897/1994 has been found, in which it is proposed to use a programmable ROM for repairing a defect in the cache memory. However, the programmable ROM in this case is a dedicated circuit element belonging to a redundancy memory control circuit in the cache memory, but represents no more than a repairing technique in the closed range of the cache memory, and has failed to adequately address our aforementioned problems, even if it is resultantly compared.
An object of the present invention is to provide a semiconductor integrated circuit device which is capable of improving the changing efficiency of a coupling change, such as a defect repair, in a circuit having a large scale logic construction, in which a nonvolatile memory made accessible by a control processing device and a volatile memory are packaged.
Moreover, an object of the present invention is to realize a cost by improving the yield of a semiconductor integrated circuit device which has been strictly demanded to have a lower cost because of its large-scale logic.
Another object of the present invention is to improve the usability of a memory module by consolidating the specifications of the defect repair of the memory module in a semiconductor integrated circuit device having a volatile memory, such as a DRAM or a SRAM, as the memory module.
Still another object of the present invention is to provide a data storage device in which there is stored design data to be used for designing a semiconductor integrated circuit device by using a computer.
The foregoing and other objects and novel features of the invention will become more apparent from the following description when taken with reference to the accompanying drawings.
Representative aspects of the invention to be described herein will be briefly summarized in the following.
A first semiconductor integrated circuit device (
1
A,
1
C) according to the invention comprises, over one semiconductor substrate: an electrically reprogrammable nonvolatile memory (
11
) capable of being accessed by a control processing device (
10
), such as a central processing unit, and a volatile memory (
12
,
13
) capable of being accessed by the control processing
Hiraki Mitsuru
Shukuri Shoji
Antonelli Terry Stout & Kraus LLP
Elms Richard
Hitachi , Ltd.
Nguyen Hien
LandOfFree
Semiconductor integrated circuit device, memory module,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, memory module,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device, memory module,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3167255