Multiple supply voltage dynamic logic

Details Multiple supply voltage dynamic logic Multiple supply voltage dynamic logic

2002-06-13

2003-11-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S098000

Reexamination Certificate

active

06646473

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system
10
includes at least a microprocessor
12
and some form of memory
14
. The microprocessor
12
has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system
10
. Specifically,
FIG. 1
shows the computer system
10
having the microprocessor
12
, memory
14
, integrated circuits (ICs)
16
that have various functionalities, and communication paths
18
, i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system
10
.
One ever-increasingly important factor that is considered in assessing the performance and operation of an integrated circuit relates to power consumption/dissipation. Power is a quadratic function of supply voltage and a linear function of the frequency at which a circuit is operated (i.e., P=0.5 CV
2
ƒ, where P represents power, C represent total capacitance, V represents supply voltage, and ƒ represents operating frequency), and thus, as integrated circuits continue to operating at ever-increasing frequencies, power consumption/dissipation becomes an important and significant concern for most circuit designers.
Integrated circuit computational blocks, such as arithmetic logic units (ALUs), are often some of the most power-consuming blocks on an integrated circuit. This is because such computational blocks are typically built using dynamic circuits in order to achieve the highest possible performance. As will be evident from the discussion below with reference to
FIG. 2
, because a dynamic circuit is heavily dependent on clock signal transitions, or other signals to which the dynamic circuit is synchronized, the dynamic circuit consumes significantly more power than those circuits that are not constantly switching between states.
FIG. 2
shows a typical dynamic circuit
45
. The operation of a typical dynamic circuit is broken into a precharge phase and an evaluation phase. In the precharge phase, the dynamic circuit is readied for the evaluation stage by some signal to which the dynamic circuit is synchronized, e.g., a clock signal. Then, in the evaluation stage, the dynamic circuit generates an output dependent on its input(s). Typical dynamic circuits are commonly used to perform logic operations such as AND, NAND, OR, and NOR logic.
As will be evident, the particular dynamic circuit
45
shown in
FIG. 2
enters a precharge phase when a clock signal, clk
50
, goes low and enters an evaluation stage when the clock signal
50
goes high. In
FIG. 2
, the clock signal
50
serves as an input to a precharge transistor
52
. When the clock signal
50
is ‘low,’ the precharge transistor
52
switches ‘on’ to precharge a dynamic node, dyn_node
54
, to Vdd
55
(i.e., ‘high’). When the dynamic node
54
is ‘high,’ a first output driver transistor
60
switches ‘on’ and drives a ‘low’ on an output, out
62
, of the dynamic circuit
45
by connecting the output
62
to ground
57
. Thus, during the precharge phase, the output
62
is low.
When the clock signal
50
goes high, i.e., enters the evaluation stage, one of two things may happen. Depending on to what value an evaluation block
56
evaluates, the dynamic node
54
is either pulled ‘low’ or left ‘high.’ For example, if the evaluation block
56
represents an OR function and is composed of n-type devices, and if one of the inputs to the evaluation block
56
is high, one of the n-type devices switches ‘on’ causing the dynamic node
54
to be driven ‘low’ by a connection to ground
57
. In this case, the ‘low’ on the dynamic node
54
switches a second output driver transistor
58
‘on,’ which, in turn drives a ‘high’ on the output
62
by a connection to Vdd
55
.
Alternatively, if none of the inputs to the evaluation block
56
are high, then the dynamic node
54
does not get connected to ground
57
, in which case, the first output driver transistor
60
continues to drive a ‘low’ on the output
62
by a connection to ground
57
. Thus, when the dynamic circuit
45
is in a precharge phase, the dynamic node
54
is readied for the evaluation stage and the output
62
is driven ‘low.’ When in the evaluation stage, the value of the output
62
depends on to what value the evaluation block
56
evaluates at the start of the evaluation phase.
Those skilled in the art will understand that similar dynamic circuitry and logic may be implemented using various evaluation block functions and structures. For example, an evaluation block for a dynamic circuit may represent an AND function and be composed of p-type devices.
As mentioned above, although dynamic circuits are highly useful and commonly used, they consume relatively high amounts of power due to their switching nature. Consequently, the proper and efficient use of dynamic circuits is of critical importance in circuit design.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit having a normal supply voltage and a reduced supply voltage comprises a clock signal selector adapted to output a first clock signal and a second clock signal dependent on a select input to the clock signal selector, and a dynamic circuit comprising: a dynamic node that, in a precharge phase, is connected to one of the normal supply voltage and the reduced supply voltage dependent on the first clock signal and the second clock signal, and an output stage, responsive to the dynamic node, having a first driver device and a second driver device, where, in an evaluation phase, one of the first driver device is selectively used to drive the normal supply voltage onto an output of the dynamic circuit and the second driver device is selectively used to drive the reduced supply voltage onto the output.
According to another aspect, an integrated circuit having a normal supply voltage and a reduced supply voltage comprises a clock signal selector adapted to output a first clock signal and a second clock signal dependent on a select input to the clock signal selector; and a dynamic circuit comprising: an input stage having an evaluation block and a dynamic node, where, in a precharge phase, the dynamic node is operatively connected to one of the normal supply voltage and the reduced supply voltage dependent on the first clock signal and the second clock signal, and where, in an evaluation phase, the dynamic node is selectively connected to ground dependent on at least one input to the evaluation block; and an output driver stage responsive to the dynamic node, where the output driver stage selectively drives one of the normal supply voltage and the reduced supply voltage onto an output of the dynamic circuit dependent on the select input.
According to another aspect, an integrated circuit having a normal supply voltage and a reduced supply voltage comprises: clock selecting means for providing a first clock signal having a first frequency and second clock signal having a second frequency, where the first frequency is greater than the second frequency; precharge means for driving a dynamic node, in a precharge phase, to one of the normal supply voltage and the reduced supply voltage dependent on the first clock signal and the second clock signal; evaluation means for evaluating at least one data input, where the dynamic node is, in an evaluation phase, dependent on the evaluation means; and output means for selectively driving one of the normal supply voltage and the reduced supply voltage onto an output dependent on the dynamic node and a select input to the clock selecting means.
According to another aspect, a method for performing dynamic circuit operations using a normal supply voltage and a reduced supply voltage comprises: selectively outputting a first clock signal having a first frequency and a second clock signal having a second frequency, where the first frequency is greater than the second frequency; in a precharge phase, precharging a dynamic node to one of the normal supply volt

Affiliated with

Also associated with

Rating

Multiple supply voltage dynamic logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple supply voltage dynamic logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple supply voltage dynamic logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3166071