Low power SRAM redundancy repair scheme

Details Low power SRAM redundancy repair scheme Low power SRAM redundancy repair scheme

2001-11-14

2003-11-04

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S200000, C365S201000

Reexamination Certificate

active

06643166

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an SRAM (Static Random Access Memory), and more particularly to an SRAM-cell power scheme.
2. Description of the Prior Art
Major design efforts have been directed at minimizing the power consumption of memory array cells. A number of solutions have been proposed, including methods to reduce overall chip power by reducing power contributed by defective memory cells.
U.S. Pat. No. 5,703,816 (Nam et al.) describes a method to reduce standby current in failed cells in an SRAM by replacing failed memory cell columns with redundant columns before packaging. A means of turning off the precharge circuit transistor pair that supplies current to the bit line pair, and also turning off the cell power line circuit for the defective column of memory array cells, is provided.
U.S. Pat. No. 6,175,938 (Hsu) discloses a scheme for reduction of standby current induced by process defects. After failing cells are replaced with redundant cells, polysilicon fuses in the VDD path for each bit line are disconnected to reduce standby current of failed cells.
U.S. Pat. No. 6,097,647 (Zagar et al.) discloses a method to electrically isolate an inoperable section of memory cells from both power and ground. This allows the remaining functional sub arrays to be utilized and eliminates the extra current draw of the defective memory cells.
Such low power memory array cells are based on a static CMOS flip-flop circuit, using a pair of cross-coupled inverters as the storage element. The steady-state power consumption of the CMOS flip-flop is naturally very small, being set by junction leakage currents. It is in this circuit, comprising the memory array cell, where power usage is critical. For a low power spec, some failing cells produce enough current for the design to exceed the chip's power spec.
What is needed is a mechanism by which defective cells can be selectively disabled, thereby reducing leakage current and overall chip power.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an efficient mechanism to minimize current contributed by failing cells in low power SRAM arrays.
It is a further object of the invention to provide a means for determining which cell or block of cells in an SRAM has a leakage path. These and other objects are achieved by an SRAM memory cell having a redundancy repair scheme, in which the SRAM memory cell has connections to an upper reference voltage and a lower reference voltage, and a means for disconnecting the SRAM memory cell from the lower reference voltage. The objects are also achieved by a method to reduce leakage current contributed by defective memory cells in an SRAM array. An SRAM is provided having a plurality of SRAM cells, each of the cells having a connection to an upper reference voltage and a lower reference voltage, testing the SRAM array for defective cells, replacing the defective cells with redundant good cells, and disconnecting the defective cells from the lower reference voltage, whereby the leakage from the defective cells is reduced, while leaving the remaining chip power scheme intact.
The lower reference voltage path is controlled by an enable signal (VSSEN), which is used to isolate defective cells under conditions indicated by array testing. This enable signal can also be used to decode which memory cells, or blocks of cells, are enabled and which defective cells are decoupled, from the low power SRAM. Gating off the path to the lower reference voltage in failing cells and replacing them with redundancy cells can reduce power contributed by defective cells. Failing redundancy cells can also be disabled, further reducing chip current and power. In this way, leakage current is minimized and overall chip power reduced.


REFERENCES:
patent: 5132929 (1992-07-01), Ochii
patent: 5703816 (1997-12-01), Nam et al.
patent: 6097647 (2000-08-01), Zagar et al.
patent: 6175938 (2001-01-01), Hsu
patent: 6333877 (2001-12-01), Nagaoka et al.

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