Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-02-22
2003-02-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06526535
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit, and particularly an integrated circuit which includes a test access port controller (TAP) for effecting communication of serial data across the chip boundary.
BACKGROUND OF THE INVENTION
An integrated circuit which includes a test access port controller is disclosed in EP-A-0840217. This document discloses an integrated circuit comprising a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data under the control of an incoming clock signal, a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation, wherein in the second mode of operation the data adaptor is supplied with parallel data and control signals from said on-chip functional circuitry and converts said parallel data and control signals into a sequence of serial bits including flow control bits and data bits for communicating off-chip via the test access port controller under the control of said incoming clock signal, said data adaptor receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits and data bits for conversion into parallel data and control signals for said on-chip functional circuitry.
The data adaptor of this integrated circuit device is intended for use with on-chip logic such as a message converter in order to observe and control the on-chip resources associated with any on-chip functional circuitry, including for example a processor. The parallel connections referred to between the data adaptor and the on-chip functional circuitry represent asynchronous interfaces between the data adaptor and the message converter. These interfaces have hitherto been asynchronous because the data adaptor and the message converter are operated under separate timing environments. Since the data adaptor and message converter are in separate clock environments, synchronisers are generally provided where the interface control signals cross clock boundaries. The accumulated delay of the synchronisers and the overheads of a safe protocol generally limit the maximum data transfer rate to 1 data transfer per 8 or so clock cycles for a byte wide parallel interface. In addition, synchronisation is usually implemented by a series of suitable storage elements, such as flip-flops, which elements are expensive in terms of the chip area consumed by the flip-flop circuits. The overall result is that the asynchronous interface between the data adaptor and the message converter imposes a limit on the maximum data transfer rate or bandwidth limitation in each direction and necessitates the inclusion of synchronisation circuitry which occupies large proportions of the chip area.
Thus it is an object of the present invention to provide a system which removes this limitation on data transfer rate.
SUMMARY OF THE INVENTION
According to an aspect of the present invention there is provided an integrated circuit comprising a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data off-chip, and a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation, wherein the data adaptor comprises a first interface for communicating data in the form of serial bits to and from said test access port controller under the control of a first clock signal and a second interface for communicating data in the form of successive sets of parallel data and control signals to and from said on-chip functional circuitry under the control of a second clock signal generated independently of said first clock signal, and wherein said data adaptor comprises data storage means for holding data received in the data adaptor to take into account differences between the first and second clock signals.
According to a second aspect of the present invention there is provided a computer system comprising an integrated circuit including a target processor connected to an on-chip bus system, functional circuitry connected to said on-chip bus system, a test access port controller connected to serial data input and serial data output pins for effecting communication of serial data across the chip boundary, and a data adaptor which is connectable to the input and output pins via the test access port controller, wherein the data adaptor comprises a first interface for communicating data in the form of serial bits to and from said test access port controller under the control of a first clock signal and a second interface for communicating data in the form of successive sets of parallel data and control signals to and from said on-chip functional circuitry under the control of a second clock signal generated independently of said first clock signal, and wherein said data adaptor comprises data storage means for holding data received in the data adaptor to take into account differences between the first and second clock signals, an off-chip host processor operable to generate and receive parallel data and control signals, and an off-chip data adaptor connected to the host processor to receive said parallel data and control signals from said host processor and to convert them into a sequence of serial bits for transmission onto the chip via the serial data input pin, and to receive a sequence of serial bits from the serial data output pin and to convert said sequence into parallel data and control signals from the off-chip host processor, whereby the host processor can communicate with said additional functional circuitry via said on-chip bus systems without involvement of the target processor.
Preferably, said data storage means comprises a receive data store operable to store data received from off-chip via said test access port controller and supply said data in the direction of said on-chip functional circuitry under the control of said second clock signal and/or a transmit data store to store data transmitted from said on-chip functional circuitry and received by said data storage means under the control of said second clock signal.
In preferred embodiments the or each data store comprises a dual port memory having a plurality of addressable storage locations, first memory access circuitry operating under the control of said first clock signal and second memory access circuitry operating under the control of said second clock signal.
Other embodiments comprise a data adaptor including two simple storage elements which assist the transfer of control and data signals in on-chip and off-chip directions, respectively. While affording fewer of the transfer rate and bandwidth advantages of the invention these embodiments provide significant design freedom in respect of various construction modules of the chip. Thus, communication across the boundary of the integrated circuit can be achieved selectively between the off-chip host processor and the functional circuitry on-chip, preferably without involving a target processor on-chip. This is particularly useful in a diagnostic environment.
In particular, embodiments allow software running on the target processor to be monitored in real time, because communication on and off-chip to the host processor can be done without interrupting real time operation of the target processor. Moreover, the use of the TAP controller and its existing serial input data pin and output data pin saves chip area and overhead in effecting the off-chip communications. The data adaptor
Chase Shelly A
De'cady Albert
Morris James H.
Skrivanek, Jr. Robert A.
STMicroelectronics Limited
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