Method of fabricating 1T1R resistive memory array

Details Method of fabricating 1T1R resistive memory array Method of fabricating 1T1R resistive memory array

2002-09-26

2003-06-24

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S382000, C438S381000

Reexamination Certificate

active

06583003

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to information storage devices, and more specifically to a memory cell array incorporating a resistive memory element.
New materials are now making it possible to produce non-volatile memory cells based on a change in resistance. Materials having a perovskite structure, among them colossal magnetoresistance (CMR) materials and high temperature superconductivity (HTSC) materials are materials that have electrical resistance characteristics that can be changed by external influences.
For instance, the properties of materials having perovskite structures, especially for CMR and HTSC materials, can be modified by applying one or more short electrical pulses to a thin film or bulk material. The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material. The pulse is of low enough energy so as not to destroy, or significantly damage, the material. Multiple pulses may be applied to the material to produce incremental changes in properties of the material. One of the properties that can be changed is the resistance of the material. The change may be at least partially reversible using pulses of opposite polarity from those used to induce the initial change.
SUMMARY OF THE INVENTION
A method of forming a 1T1R resistive memory array is provided. The method comprises forming an array of transistors on a substrate. The transistors may be formed using a process suitable for the formation of both the array of transistors as well as transistors used in at least some of the support circuits. Support circuits are defined here as any non-memory devices, which may be connected to the resistive memory array, such as coding, decoding, data processing or computing circuitry. The transistors comprise a polycide/oxide
itride gate stack with nitride sidewalls. A silicon oxide insulation layer is deposited and planarized, for example using CMP, to the level of the gate stack. Photoresist is used to form a bit contact pattern. Bit contact openings are then opened to expose the drain regions of the transistors. A metal, such as Pt or Ir, is then deposited and planarized to the level of the gate stack to form bottom electrodes. A layer of resistive memory material is then deposited over the bottom electrodes, and possibly over the entire array of transistors. Top electrodes are then formed over the resistive memory material.
Using the present method, it may be possible to form a resistive memory array without adding a significant number of additional steps, as the process steps associated with the formation of support circuits can be used to form the array of transistors that form the resistive memory array.


REFERENCES:
patent: 5847442 (1998-12-01), Mills et al.
patent: 6204139 (2001-03-01), Liu et al.
Article entitled, “Electric-Pulse-Induced Reversible Resistance Change effect in Manetoresistive Films”, by S. Q. Liu et al., published in Applied Physics Letters, vol. 76, No. 19, pp 2749-2751.
Article entitled, “Reproducible Switching Effect in Thin Oxide Films for Memory Applications”, by A. Beck et al., published in Applied Physics Letters, vol. 77, No. 1, Jul. 3, 2000, pp 139-141.

Affiliated with

Also associated with

Rating

Method of fabricating 1T1R resistive memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating 1T1R resistive memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating 1T1R resistive memory array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3162120