Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-11
2003-12-23
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S203000, C438S204000, C438S205000, C438S234000, C438S236000, C438S322000, C257S370000, C257S371000, C257S372000
Reexamination Certificate
active
06667202
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device formed combining a bipolar transistor with a complementary field-effect transistor (hereinafter referred to as ‘CMOS’) and a method for making the same.
BACKGROUND OF THE INVENTION
BiCMOS having a bipolar transistor and CMOS formed on a common substrate has both the high-speed operation and high driving performance of bipolar transistor and the low consumed power of CMOS. Thus, BiCMOS is one of the most effective means to meet recent demands for low consumed power and high-speed operation.
H. Suzuki et al., “Process Integration Technologies for a 0.3 &mgr;m BiCMOS SRAM with 1.5V Operation”, IEEE, Proceedings of the 1996 Bipolar/BiCMOS Circuits and Technology Meeting, pp.89-92 (hereinafter referred to as ‘first prior art’) reports a bipolar transistor structure of BiCMOS.
In the first prior art (BiCMOS), the n
+
-type buried layer must be diffused in the horizontal and vertical directions of the wafer due to the following three processes:
1) high-temperature thermal treatment in growing the epitaxial layer,
2) thermal treatment in forming the device-separating oxide film, and
3) thermal treatment for reducing the collector resistance.
Namely, these high-temperature thermal treatments prevent the size of bipolar transistor from being reduced.
Furthermore, in the first prior art, there is an essential problem that the number of fabrication steps must be increased since it needs to form the n
+
-type buried layer and n-type epitaxial layer which are not necessary for CMOS.
In this regard, K. Ishimaru et al., “Bipolar Installed CMOS Technology without Any Process Step Increase for High Speed Cache SRAM”, Technical Digest of International Electron Devices Meeting 1995, pp.673-676 (hereinafter referred to as ‘second prior art’) gives a solution to the above problems as to the transistor size and the number of BiCMOS fabricating steps.
In the second prior art, the n
+
-type buried layer and epitaxial layer are not formed and the collector region is formed by the ion implantation at high energy. As a result, the problem that the transistor size is prevented from being decreased because of the unnecessary expansion in impurity region due to thermal hysteresis can be solved. Also, the essential problem that the number of fabrication steps of BiCMOS is too many can be solved by having some of the steps of fabricating CMOS and bipolar transistor in common.
However, in the second prior art, there occurs a new problem that the collector resistance is increased to six times, 300
&OHgr;
, compared with 50
&OHgr;
of conventional BiCMOS, as described in Table 1 in the second prior art. The collector resistance has to be compared between transistors with a same size since it depends upon the transistor size. In experimenting on a transistor with a same size as that in the first prior art, a collector resistance of 450
&OHgr;
is obtained.
On the other hand, the essential problem that the number of fabrication steps of BiCMOS is too many can be also solved by the following method. A through-process of BiCMOS is, in general, designed by combining a bipolar transistor into the process of fabricating CMOS as a base process or combining CMOS into the process of fabricating a bipolar transistor as a base process.
Accordingly, the essential problem can be solved by reducing the number of steps in the base process or the process for the component to be combined.
A specific example of such a method is disclosed in U.S. Pat. No. 5,358,882 (hereinafter referred to as ‘third prior art’) that the number of steps in fabricating a bipolar transistor is reduced.
As described above, in the first prior art, there is the problem that the size of bipolar transistor is prevented from being reduced because the n
+
-type buried layer must be diffused in the horizontal and vertical directions of the wafer. Also, there is the essential problem that the number of BiCMOS fabrication steps must be increased.
In the second prior art, which can help solve these problems, there is the problem that the collector resistance of the bipolar transistor is increased because the collector region formed by the ion implantation must have a lowered impurity concentration.
Problems caused by an increase in collector resistance will be explained in FIG.
4
.
FIG. 4
shows a DC characteristics dependency to collector resistance in applying a voltage of 1.0V between the collector and emitter of a bipolar transistor. In
FIG. 4
, full lines indicate a characteristic in case of a collector resistivity of 200 &OHgr;, and dotted lines indicate a characteristic in case of a collector resistivity of 300 &OHgr;. As seen from the dotted lines in
FIG. 4
, in case of a collector resistivity of 300 &OHgr;, base current (I
B
) is rapidly increased, compared with collector current (I
C
), in a range of high base-to-emitter voltage (V
BE
>1.0V). Thereby, the current-amplification factor (=I
C
/I
B
) of the bipolar transistor is rapidly decreased. In general, this phenomenon is called ‘saturation’, and it is know that such a phenomenon affects badly the circuit operation.
In the third prior art, the number of BiCMOS fabrication steps can be reduced without increasing the collector resistance. However, in the third prior art, the n
+
-type buried layer formed on the p-type silicon substrate must be diffused, like the first prior art, in the horizontal direction due to the high-temperature thermal treatment in growing the epitaxial layer on the n
+
-type buried layer. Because of this, the insulation separation width of the bipolar transistor must be increased, therefore preventing the transistor size from being reduced.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor device and a method for making a semiconductor device that the number of fabrication steps can be reduced and the size of bipolar transistor can be miniaturized without increasing a collector resistance.
According to the invention, a semiconductor device, comprises:
a bipolar transistor comprising a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region;
a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region;
a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and
a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.
According to another aspect of the invention, a semiconductor device, comprises:
a bipolar transistor comprising a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region;
a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region;
a collector connection region that is formed in the collector extraction region and a second conductivity type of impurity is implanted with a concentration higher than the collector region;
a concave portion in the collector connection region that is formed up to a depth where the collector connection region or collector region has a peak concentration in impurity distribution; and
a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.
According to another aspect of the invention, a semiconductor device, comprises:
a bipolar transistor comprising a coll
Fahmy Wael
NEC Electronics Corporation
Rao Shrinivas H
Sughrue & Mion, PLLC
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