Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-12-28
2003-06-03
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S760020
Reexamination Certificate
active
06574763
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits and more specifically to a method and apparatus for semiconductor integrated circuit testing and burn-in.
BACKGROUND OF THE INVENTION
To increase device yield, semiconductor integrated circuits such as DRAM and SRAM memories employ redundant circuitry that allows the integrated circuits to function despite the presence of one or more manufacturing or other defects (e.g., by employing the redundant circuitry rather than the original, defective circuitry). For example, conventional DRAM and SRAM memories often use laser fuse blow techniques as part of their redundancy scheme wherein redundant circuitry may be employed in place of defective circuitry by blowing one or more fuses with a laser beam.
While laser fuse blow techniques improve device yield, several problems remain. Laser fuse blow techniques must be performed at the wafer level and thus are time consuming and costly. For example, a wafer typically must leave a test station for fuses to be blown, and then return to the test station for verification. For DRAM memories, 80% of post burn-in module fallout yield loss can be due to single cell bit fails. However, while single cell bits fails are recoverable with redundancy, laser fuse blow techniques cannot be applied to modules.
To address the limitations of laser fuse blow techniques, electronic fuses and antifuses have been developed which may be electronically blown at the module level. For example, U.S. patent application Ser. No. 09/466,495 (titled “ANTIFUSES AND METHODS FOR FORMING THE SAME”) and U.S. patent application Ser. No. 09/466,479 (titled “METHODS AND APPARATUS FOR BLOWING AND SENSING ANTIFUSES”), both incorporated by reference herein in their entirety, disclose antifuse structures and circuitry for blowing/sensing antifuses, respectively. Such antifuse structures and related circuitry are particularly useful for eliminating single cell bit fails in DRAM memories.
In order to repair integrated circuitry defects, defects must first be identified. However, conventional defect identification approaches often cannot identify certain early-life defects, such as “self-healing” defects which appear at elevated temperatures (e.g., above 120° C.) or below ambient temperatures (e.g., about 10° C.), but which do not appear at the operating temperatures typically used for blowing fuses and antifuses (e.g., about 85° C.). Accordingly, a need exists for an improved method and apparatus for semiconductor integrated circuit testing and burn-in that can identify and correct circuitry defects, including self-healing defects and other early life defects.
SUMMARY OF THE INVENTION
To overcome the needs of the prior art, an improved method and apparatus are provided for semiconductor integrated circuit testing and burn-in that can identify and correct circuitry defects, including self-healing defects and other early life defects. Specifically, an inventive method and apparatus are provided that significantly increase the capabilities of a conventional burn-in oven to detect early life defects.
In a first aspect of the invention, a burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ (e.g., while within a burn-in oven), and lowering the temperature of the memory array to ambient temperature to complete the burn-in process of the memory array.
In a second aspect of the invention, an apparatus for carrying out the above process is provided. The apparatus includes a test circuit adapted to couple to a memory array and that generates a test pattern and applies the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response of the memory array to the test pattern to an expected response of the memory array to the test pattern, and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.
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Bertin Claude L.
Hedberg Erik L.
Houghton Russell J.
Tonti William R.
Chase Shelly A
De'cady Albert
DeLio & Peterson LLC
International Business Machines - Corporation
Peterson Peter W.
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