Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-17
2003-10-21
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000
Reexamination Certificate
active
06635921
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention is directed to a semiconductor memory device having a multiple tunnel junction layer pattern and a method of fabricating the same.
2. Description of the Related Art
An advantage of a dynamic random access memory (DRAM) device is a higher integration density than other memory devices, such as a static random access memory (SRAM). However, in case of the DRAM, a periodic refresh is necessary to retain data stored in the memory cell. Therefore, electric power is consumed even when the device is in a stand-by mode. Alternatively, in a case of a non-volatile memory device, such as a flash memory device, the refresh operation for the stored data is basically unnecessary. Unfortunately, a non-volatile memory device requires a high voltage to program or erase memory cells.
FIG. 1
illustrates a cross-sectional view of a conventional semiconductor memory device having a multiple tunnel junction layer pattern.
Referring now to
FIG. 1
, a unit cell of a semiconductor memory device includes a planar transistor and a vertical transistor. The planar transistor includes a drain region
17
d
and a source region
17
s
, which are separately formed in predetermined regions of a semiconductor substrate
1
, and a floating gate
5
located over a channel region between the drain region
17
d
and the source region
17
s
. The drain region
17
d
and the floating gate
5
correspond to a bitline and a storage node, respectively. A gate insulating layer
3
is interposed between the storage node (i.e., the floating gate)
5
and the channel region.
A multiple tunnel junction layer pattern
12
and a data line
13
are sequentially stacked on the storage node
5
. The multiple tunnel junction layer pattern
12
includes semiconductor layers
7
and tunnel insulating layers
9
that are alternately and repeatedly stacked. A top layer
11
of the multiple tunnel junction layer pattern
12
may be a semiconductor layer
7
or a tunnel insulating layer
9
. The data line
13
is extended for electrically connecting a plurality of adjacent memory cells. The storage node
5
, the multiple tunnel junction layer pattern
12
, and the data line
13
constitute a multi-layered pattern
15
.
A sidewall and a top surface of the multi-layered pattern
15
are covered with an inter-gate insulating film
19
. A wordline
21
is formed on the inter-gate insulating film
19
across the data line
13
. The wordline
21
is formed to overlap the multi-layered pattern
15
. The data line
13
, the multiple tunnel junction layer pattern
12
, the storage node
5
, the inter-gate insulating film
19
, and the wordline
21
constitute the vertical transistor.
In the above-described conventional semiconductor memory device, an overlapping area between the storage node and the wordline is directly related to the thickness of the storage node. The overlapping area has an influence upon the coupling ratio of the unit cell. That is, an increase in the overlapping area leads to an increase in the coupling ratio. Thus, it is necessary to increase the overlapping area between the storage node and the wordline in order to reduce a read voltage applied to the wordline in a read mode. However, if the thickness of the storage node is increased for increasing the overlapping area, the height of the unit cell is increased, which results in a difficulty in performing a subsequent patterning process.
SUMMARY OF THE INVENTION
A primary features of an embodiment of the present invention provides a semiconductor memory device having a high coupling ratio without an increase in the height of a unit cell.
Another feature of an embodiment of the present invention provides a semiconductor memory device that achieves an excellent read operation with a low read voltage.
Still another feature of an embodiment of the present invention provides a method of fabricating a semiconductor memory device that may increase a coupling ratio within a limited height of a unit cell.
Yet another feature of an embodiment of the present invention provides a method of fabricating a semiconductor memory device that may reduce the read voltage.
These and other features of the present invention are accomplished by a semiconductor memory device having a multiple tunnel junction layer pattern and a fabricating method thereof. A unit cell of the semiconductor memory device includes a planar transistor and a vertical transistor. The planar transistor includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, and a storage node formed on a channel region between the first and second conductive regions. A gate insulating layer pattern may be interposed between the storage node and the substrate. The vertical transistor includes the storage node, a multiple tunnel junction layer pattern stacked on the storage node, a data line disposed on the multiple tunnel junction layer pattern and parallel to the first and second conductive regions, and a wordline crossing over the data line and covering both sidewalls of the storage node and both sidewalls of the multiple tunnel junction layer pattern. An inter-gate insulating film may be interposed between the wordline and sidewalls of the storage node, and between the wordline and sidewalls of the multiple tunnel junction layer pattern. Both sidewalls of the storage node include an undercut region for maximizing a overlapping area between the storage node and the wordline.
The semiconductor memory device according to an embodiment of the present invention may also include a plurality of parallel conductive regions formed on a semiconductor substrate, a plurality of storage nodes having undercut sidewalls, trench regions formed in the semiconductor substrate between the storage nodes arranged on a line parallel to the conductive regions, a plurality of multiple tunnel junction layer patterns, device isolation layer patterns filling the trench regions, a plurality of data lines covering the multiple tunnel junction layer patterns and the device isolation layer patterns therebetween on a line parallel to the conductive regions, and a plurality of parallel wordlines.
To maximize the overlapping area between a wordline and a storage node, the storage node is formed by alternately and repeatedly stacking first and second conductive layer patterns. The width of all first conductive layer patterns in the stack, in a direction parallel to the wordline direction is smaller than the width of all second conductive layer patterns and the width of the multiple tunnel junction layer pattern.
The storage node acts as a source region of the vertical transistor, as well as a gate electrode of the planar transistor. This makes it possible to maximize a capacitance between the storage node and the wordline within a limited height of the storage node. In other words, a coupling ratio of the unit cell may be maximized. This feature results in a decrease in read voltage applied to the wordline in a read mode.
A method of fabricating a semiconductor memory device according to an embodiment of the present invention includes forming a gate insulating layer pattern, a storage node pattern, a multiple tunnel junction layer pattern, an upper conductive layer pattern, and a data line that are sequentially stacked on a predetermined region of a semiconductor substrate. The data line is extended in one direction. The storage node pattern is formed by alternately and repeatedly stacking at least two conductive layers having different etch rates. The storage node pattern is etched to form a storage node having a sidewall with an undercut region. Thus, a sidewall area of the storage node is maximized. An inter-gate insulating film may be conformally formed on an entire surface of a semiconductor substrate having the storage node. A wordline is formed on the inter-gate insulating film, if present, across the data
Kim Woo-Sik
Yi Ji-Hye
Lee & Sterba, P.C.
Prenty Mark V.
Samsung Electronics Co,. Ltd.
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