Integrated circuit device and module with integrated circuits

Details Integrated circuit device and module with integrated circuits Integrated circuit device and module with integrated circuits

2002-07-10

2003-12-23

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S189020, C365S189070, C257S737000

Reexamination Certificate

active

06667895

ABSTRACT:

This application claims benefit and priority of Korean Patent Application No. 2001-76944, filed Dec. 6, 2001.
BACKGROUND OF THE INVENTION
Conventional integrated circuits include a variety of active and passive electrical components. The active electrical components may comprise, e.g., diodes and transistors. The passive components may include, e.g., capacitors and resistors.
Integrated together upon a substrate, the electrical elements can provide combined electrical functionality. For example, the integrated elements might be used to provide memory as a dynamic random access memory (DRAM) or static random access memory (SRAM). Additionally, a plurality of such integrated memory chips may be assembled together to provide a memory module of larger capacity memory.
Most memory modules use a plurality of integrated circuits mounted on both sides of a module board, such as a printed circuit board. For example, a plurality of memory chips—such as chip scale, gull wing, flip-chip, ball grid array or other package configuration—may be mounted to opposite surfaces of the module board. The board provides the physical support to the integrated circuits. Additionally, it may electrically couple terminals of the integrated circuits and external circuits.
A dual in-line memory module (DIMM) may comprise a plurality of memory chips mounted to opposite surfaces of a printed circuit board. To simplify, a wiring layout for the module board for chips that oppose one another of the opposite sides may have pin assignments of mirrored relationship. The chips for one side of the board may have terminals (i.e., pins) of mirrored relationship relative to those of similar identity on the opposite side of the board. Such mirrored chips may be referred to as “mirrored pairs” or “mirror images.”
When positioned opposite one another on opposite sides of a module board, the terminals of same identity of the two opposing chips of a mirror may be interconnected at substantially the same locations on the board. Accordingly, the board layout may be simplified and the lengths of its conductive traces may be kept short.
It may be understood that as the integrated circuit densities increase, the integrity of interconnections and signal routing may be affected. The increased densities may reduce line geometries, which in-turn may increase circuit RC settling constants and propagation delays. Regardless, manufactures continue to push for increased densities.
In addition to seeking greater densities, many manufactures strive to provide for integrated circuit devices that may achieve substantially the same propagation delays across a plurality of its interfaces—e.g., interfaces which may be associated with board-to-package transitions and internal I/O lines of the device. If the electrical delays (i.e., lengths or propagation paths) of the plurality of interfaces may be kept substantially the same, device manufactures may be able to provide devices of higher operating speeds and greater I/O capability than what might otherwise be available. This may be especially valuable for development of memory modules for multi-bit and synchronous data transfer applications.
SUMMARY
In accordance with an exemplary embodiment of the present invention, an integrated circuit device comprises a substrate having circuitry integrated together with the substrate. A switching circuit is selectably operable to configure first and second signal paths of respective first and second pads, the first and second pads of mirrored relationship about an axis of the substrate. In accordance with a select signal, the switching circuit may alternatively configure the first signal path between the first pad and one node of first and second internal nodes, and the second signal path between the second pad and the other node of the first and second internal nodes. At least one of the first and second signal paths may comprise a buffer positioned electrically in series between the switching circuit and the respective first or second pad.
In a further exemplary embodiment, the buffer may comprise a signal converter to convert signals of TTL levels to CMOS levels.
In another exemplary embodiment, the buffer may present an impedance match to a transmission path associated with the first or second pad.
In yet a further aspect of an exemplary embodiment, a plurality of the mirrored pair of first and second pads may be associated with corresponding mirrored pins of a ball grid array.


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patent: 6370054 (2002-04-01), Fujisawa et al.
patent: 2000-340737 (2000-12-01), None

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