Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-31
2003-10-21
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S342000, C257S343000, C257S345000, C257S328000, C257S336000
Reexamination Certificate
active
06635925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to a technique of an LD (Lateral Double diffused) MOS transistor structure serving as a high withstand voltage element that is applied to e.g. an IC for driving liquid-crystal.
2. DESCRIPTION OF THE RELATED ART
Now referring to the drawings, an explanation will be given of a conventional semiconductor device and a method of manufacturing it. The above DMOS transistor structure refers to an element in which impurities of a different conduction type are diffused into a diffused layer previously formed on the surface side of a semiconductor substrate to form new diffused layers and a difference of diffusion in the lateral direction between the diffused layers is used as an effective channel length. A channel length can be shortened and hence is suited to realize a low ON-resistance.
FIG. 6
is a sectional view for explaining a conventional DMOS transistor illustrated in an N-channel type DMOS transistor structure. Although no explanation will be given of a P-channel type DMOS transistor structure, as well known, it can have the same structure as the N-channel type DMOS transistor structure.
In
FIG. 6
, reference numeral
51
denotes a semiconductor substrate of first conduction type, e.g. P-type. Reference numeral
52
denotes an N-type well within which a P-type body layer
53
is formed. An N-type diffused layer
54
is formed within the P-type body layer
53
. An N-type diffused layer
55
is formed within the,N-type well
52
. A gate electrode
57
is formed on a substrate surface through a gate oxide film
56
. A channel layer
58
is formed in the surface layer of the P-type body layer
53
immediately below the gate electrode
57
.
The N-type diffused layer
54
serves as a source diffused layer, the N-type diffused layer
55
serves as a drain diffused layer and the N-type well
52
below a LOCOS oxide film
59
serves as a drift layer. Reference numerals
60
and
61
denote-a source. electrode and a drain electrode, respectively. Reference numeral
62
denotes a P-type diffused layer for taking the potential of the P-type body layer
53
. Reference numeral
63
denotes an interlayer insulating film.
An explanation will be given of a method of manufacturing the above DMOS transistor structure. N-type impurities are ion-implanted into the semiconductor substrate
51
to form the N-type well
52
. After the gate oxide film
56
has been formed on the substrate
51
, the gate electrode
57
is formed through the gate oxide film
56
. Using the gate electrode
57
as a mask, the P-type impurities are ion-implanted and diffused to form the P-type body layer
53
. Thereafter, the N-type diffused layers
54
and
55
are formed.
In the DMOS transistor described above, since the N-type well
52
is formed by diffusion, the dopant concentration on the surface of the N-type well
52
becomes high, thereby facilitating a current flow on the surface of the N-type well
52
and realizing high withstand voltage. The DMOS transistor having the structure described above is referred to as a relaxing-surface type (Reduced SURface Field: RESURF) DMOS in which the dopant concentration of the drift layer of the N-type-well
2
is set so as to satisfy the RESURF requirement. Such technology is disclosed in JP-A-9-139438.
The above DMOS transistor -structure presents a problem when the P-channel type DMOS transistor is structured.
Specifically, the conductive film constituting a gate electrode is often of the N conduction type. In this case, the driving capability of the P-channel type DMOS transistor is inferior to that of the N-channel type DMOS transistor.
In order to obviate such inconvenience, a high voltage must be applied to improve the switching characteristic. This goes against the tendency of realization of low-voltage
SUMMARY OF THE INVENTION
The first object of the present invention is to provide a P-channel type DMOS transistor, especially a P-channel type DMOS transistor with improved driving capability.
The second object of the present invention is to provide a method of manufacturing a DMOS transistor, especially a P-channel type DMOS transistor.
In order to attain the above object, in accordance with the present invention, there is provided a P-channel type DMOS transistor comprising heavily doped source/drain layers formed in an N-type well, a gate electrode formed on a channel layer located between the source/drain layers, an N-type body layer formed in the vicinity of the source layer, and a lightly-doped drain layer formed between the channel layer and the drain layer, wherein a P-type layer is formed in the channel layer at the upper part of the N-type body layer.
Further, there is provided a method of manufacturing a semiconductor device comprising the steps of ion-implanting P-type impurities into an N-type well to form a (first )lightly-doped drain layer (P-layer), ion-implanting P-type impurities into the N-type well to form a SLP (second lightly-doped drain layer shallow low impurity concentration P type) layer so as to be adjacent to the P-type drain layer ion-implanting the P-type impurities into the N-type well to form heavily-doped P-type source/drain layers and thereafter ion-implanting the N-type impurities into the N-type well to form an N-type body layer so as to pass through the SLP layer and to be adjacent to the P-type source layer, ion-implanting the P-type impurities into the N-type well to form a P-type layer in a channel layer formed at the upper part of the body layer; and forming a gate electrode
18
on the N-type well through a gate oxide film
As an improved method, there is provided a method of manufacturing a semiconductor device comprising the steps of forming a second lightly-doped drain layer (P-layer) by ion-implanting P-type impurities into an N-type well, after forming a first lightly-doped drain layer (P-layer)
5
so as to be adjacent to the P-type drain layer, and then to form simultaneously a P-type layer in a channel layer. And thereafter ion-implanting the N-type impurities into the N-type well to form an N-type body layer so as to pass through the SLP layer and to be adjacent to the P-type source layer. According to the above method, the step of ion-implanting P-type impurities to form the P-type layer in a channel layer can be reduced.
Further in the above DMOS transistor, by forming a impurity region for controlling the driving capability, in each of the channel regions corresponding to each conduction type of transistors, the driving capability of each conduction type of transistors formed in a same substrate can be made substantially equal to each other. The above technology can be applicable to opposite conduction type of transistor or same conduction type of transistor.
In accordance with the invention, by forming the thin P-type impurity layer in the channel layer, the driving capability of the P-channel type DMOS transistor that is inferior to that of the N-channel type DMOS transistor can be improved.
The manufacturing method according to the invention, in which all the impurity layers have been formed before the gate electrode is formed, can provide the P-channel DMOS transistor having the structure described above.
REFERENCES:
patent: 4597824 (1986-07-01), Shinada et al.
patent: 5449937 (1995-09-01), Arimura et al.
patent: 5536957 (1996-07-01), Okumura
patent: 6147383 (2000-11-01), Kuroda
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 405251697 (1993-09-01), None
Aoyama Masashige
Arai Takashi
Taniguchi Toshimitsu
Fish & Richardson P.C.
Lee Eddie
Nguyen Joseph
Sanyo Electric Co,. Ltd.
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