Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-11-30
2003-10-14
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S502000, C713S600000
Reexamination Certificate
active
06633989
ABSTRACT:
CROSS-REFERENCE TO SOURCE CODE APPENDIX
Appendix A, which is part of the present disclosure, contains VERILOG source code for implementing one embodiment of this invention as described more completely below.
A portion of the present disclosure contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND
IEEE Standard for a High Performance Serial Bus (“IEEE 1394”) provides that each isochronous-capable node must implement, among others, a CYCLE_TIME register storing a 32 bit time signal (“CYCLE_TIME”) updated by a free-running 24.576 MHz clock. An isochronous-capable node is a device that can transfer isochronous data over a serial bus to other isochronous-capable nodes. In isochronous data transfer, data is broadcasted on assigned channels with guaranteed bandwidth allocation.
Signal CYCLE_TIME in the CYCLE_TIME register comprises a seven bit second_count field, a thirteen bit cycle_count field, and a twelve bit cycle_offset field. The cycle_offset field increments on each tick of the 24.576 MHz clock with the exception that an increment from the value of 3071 causes a wraparound to zero and a carry into the cycle_count field. The cycle_count field increments on each carry from the cycle_offset field with the exception that an increment from the value of 7999 causes a wraparound to zero and a carry into the cycle_count field. The second_count field increments on each carry from the cycle_count field with the exception that an increment from the value of 127 causes a wraparound to zero.
The CYCLE_TIME register must further be synchronized to a time signal (“MASTER_TIME”) contained in a cycle start packet (“CSP”) transmitted by a node known as the master node. Specifically, IEEE 1394 standard provides that “a cycle slave must implement a synchronization mechanism between the cycle start packets and the CYCLE_TIME register such that time, as observed by the values of the CYCLE_TIME register, never appears to move backwards.” IEEE Standard for a High Performance Serial Bus, p.212, The Institute of Electrical And Electronics Engineers, Inc., 1996. However, the details of the synchronization mechanism are left to the individual device manufacturers.
The IEEE 1394 standard is available from the Institute of Electrical and Electronic Engineers located at 345 East 47th Street, New York, N.Y. 100107-2394. The IEEE 1394 can be purchased directly from the IEEE. The IEEE 1394 standard is hereby incorporated by reference in its entirety.
An implementation of IEEE 1394 standard includes a first node
600
and a second node
700
coupled through a cable
614
(FIG.
1
A). Node
600
includes an application logic
602
, a link controller
604
, and a PHY chip
606
. Circuitry included in application logic
602
(
FIG. 1B
) depends on the application. For example, for a set top box, logic
602
includes RF tuner, IF tuner, forward error correction circuit, MPEG2 transport stream decoder, MPEG2 video decoder, MPEG2 audio decoder, smartcard interface, and memory (ROM and RAM). Similarly, node
700
includes another application logic
702
, a link controller
704
, and a PHY chip
706
. Link controller
604
(
FIG. 1B
) includes a packet transmitter
608
, a packet receiver
610
, and a cycle control
612
. Cycle control
612
includes a register
603
conforming to the IEEE 1394 standard. PHY chip
606
also includes, for example, 24.576 MHz clock
616
. Note that when node
600
is in master mode, packet transmitter
608
uses the value of register
603
to generate a cycle start packet, as described in the IEEE 1394 standard.
SUMMARY
In accordance with the present invention, a circuit for synchronizing a first time signal to a second time signal includes a first timer, a second timer, and a comparator. The first timer repetitively increments (once during each clock cycle) the first time signal and drives the first time signal on an output bus of the first timer. The second timer saves a time signal from a master node as a second time signal and drives the second time signal on an output bus of the second timer. The comparator is coupled to the output bus of the first timer and the output bus of the second timer. The comparator compares the first time signal and the second time signal. When the second time signal is less than the first time signal, the first timer stops incrementing the first time signal, i.e., freezes the first time signal. At the same time, the second timer starts to repetitively increment (once during each clock cycle) the second time signal. As before, the second timer continues to drive the second time signal on the output bus of the second timer. When the second time signal is equal to the first time signal, the first timer starts again to repetitively increment and drive the first time signal on the output bus of the first timer. At the same time, the second timer stops incrementing the second time signal.
In one embodiment of the present invention, the first timer includes a first register coupled to a first multiplexer, together hereafter referred to as a “first selective register.” The first timer also includes an incrementor coupled to a second multiplexer, together hereafter referred to as a “selective incrementor.” To increment the first time signal, the output bus of the first register is coupled to input port of the incrementor through the second multiplexer and the output bus of the incrementor is coupled to the input port of the first register. To freeze the first time signal, the output bus of the first register is coupled to the input port of the first register through the first multiplexer.
In another embodiment, the second timer includes a second register coupled to a third multiplexer, together hereafter referred to as a “second selective register,” and also includes the selective incrementor (described above). To increment the second time signal, the output bus of the second register is coupled to input port of the incrementor through the second multiplexer and the output bus of the incrementor is coupled to the input port of the second register through the third multiplexer. In one embodiment, the first timer and the second timer use separate incrementors to increment the first time signal and the second time signal, respectively. In another embodiment, the first timer and the second timer use a single incrementor to increment the first time signal and the second time signal.
REFERENCES:
patent: 4588884 (1986-05-01), Priscott
patent: 5001730 (1991-03-01), Franaszek et al.
patent: 5442773 (1995-08-01), Oto
patent: 5555383 (1996-09-01), Elazar et al.
patent: 5577235 (1996-11-01), Mitra
patent: 5918040 (1999-06-01), Jarvis
patent: 5926048 (1999-07-01), Greatwood
patent: 6028412 (2000-02-01), Shine et al.
patent: 6047382 (2000-04-01), Maley et al.
patent: 6195758 (2001-02-01), Lundh et al.
patent: 356065547 (1981-06-01), None
patent: 401136441 (1989-05-01), None
IEEE Standard for a High Performance Serial Bus, IEEE Std. 1394-1995, Aug. 30, 1996, pp. 199-348.
International Standard CEI/IEC 61883-1:1998, pp. 3-83.
International Standard CEI/IEC 61883-4:1998, pp. 3-23.
Cao Chun
Lee Thomas
LSI Logic Corporation
Maioriana, PC Christopher P.
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