Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-09-01
2003-02-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S755000, C714S786000
Reexamination Certificate
active
06516441
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data communication device and method for a communication system, and in particular, to a frame constructing device and method for transmitting data on a subframe unit basis.
2. Description of the Related Art
As used herein, the term “data bit” refers to uncoded data, and the term “symbol” refers to data coded by a channel coder.
In communication systems for processing voice, character, image and video signals, data is generally transmitted on a frame unit basis. A frame is defined as a basic timing interval in the system. In a communication system employing packet switched transmission, throughput represents a ratio of the number of error-free frames to the number of the total received frames. When data is transmitted over a very long frame within a bad channel environment, error frames increase in number, thus reducing the throughput. In addition, the complexity of a receiver is proportional to the number of calculations performed, which is dependent on the length of the received frames. Therefore, in considering the reduced throughput experienced due to channel environment and receiver complexity, a method for dividing a frame into subframes and transmitting data using an ARQ (Automatic Repeat Request) technique is required.
However, a communication system which provides not only a voice service but also various data services, uses a channel coder having different features according to data rates and a service options. In particular, a convolutional coder is typically used for low rate transmission of voice and data, and a turbo coder is typically used for high rate data transmission. Further, in a system for communicating the frame data, a channel encoder for error correction should also encode data on the frame unit basis. In this case, the channel coder adds zero bits at the tail end of the sequence to indicate the termination of each frame so that a decoder can efficiently decode the frames using that information. An IS-95 system typically uses a non-recursive systemic convolutional coder, which adds a sequence of zero (0) bits to the end of each frame, equal to the number of delays, to implement frame termination.
Meanwhile, a typical turbo coder is comprised of two serial or parallel connected systemic convolutional coders and a turbo interleaver connected between the two systemic convolutional coders. Particularly, in a systemic convolutional coder used for a constituent coder of the turbo coder, termination is not implemented even though a sequence of zero bits are added to input data bits equal to the number of delays, in contrast to the non-recursive systemic convolutional coder. This is because the input data bits are fed back to the delays. The systemic convolutional coder employs a termination method using a feedback value and a method for performing decoding without termination. For more detailed information, see Mark C. Reed and Steven S. Pietrobon, “Turbo-Code Termination Schemes and a Novel Alternative for Short Frames”, PIMRC '96, Oct. 15-18, 1996.
A relationship between a signal-to-noise ratio (SNR), and a bit error rate (BER) and a frame error rate (FER) depends on the type of the channel coder. For example, in a turbo coder, SNR required to maintain BER or FER is permitted to be lower, when the frame size (or length) becomes longer. However, in a convolutional coder, SNR required to maintain BER is relatively constant regardless of the frame size, whereas FER increases as the frame increases in size. Therefore, a subframe constructing method for minimizing performance of a communication system which uses two channel coders having different features is required.
It will be assumed herein that a convolutional coder has a constraint length K=9 and a coding rate R=1/3, and a turbo coder has a constraint length K=4 and a coding rate R=1/3.
FIG. 1
illustrates a conventional layered frame structure, in which subframes are taken into consideration. Here, a convolutional coder is used for a channel coder. The frame of
FIG. 1
includes 4 layers of an interleaver block
101
, a physical layer frame
102
, a channel coding block
103
and an ARQ block
104
. The interleaver block
101
may include several physical layer frames
102
; contrariwise, the physical layer frame
102
may include several interleaver blocks
101
. However, it will be assumed herein that one interleaver block
101
constitutes one physical layer frame
102
. The physical layer frame
102
may include several channel coding blocks
103
, and the channel coding block
103
may include several ARQ blocks
104
. Each ARQ block
104
is comprised of data bits and zero (0) bits. For better understanding, a description will be made with reference to a case where a data rate of 38.4 Kbps is used. Hereinafter, it will be assumed that a CRC (Cyclic Redundancy Code) is comprised of 16 bits.
When the ARQ block
104
is a single ARQ block, the ARQ block
104
includes N (=744) data bits, 16 CRC bits and 8 tail bits, so that the frame is comprised of 768 bits in total. However, when the ARQ block
104
is comprised of two subblocks of first and second ARQ blocks
104
-A and
104
-B, the first ARQ block
104
-A includes 360 first data bits
111
, 16 first CRC bits
112
and 8 first additional bits
113
, and the second ARQ block
104
-B includes 360 second data bits
121
, 16 second CRC bits
122
and 8 convolutional tail bits
123
, so that the frame is comprised of 768 bits in total. However, in either case, the number of data bits input to the channel coding block
103
is fixed to 768, and the number of channel coded symbols for the 768 data bits becomes 768×3=2304. In the case where the ARQ block
104
is comprised of the first and second ARQ blocks
104
-A and
104
-B, the frame additionally includes the 16 first CRC bits
112
and the 8 first additional bits
113
, undesirably causing an increase in overhead. However, it is advantageous in that retransmission can be performed using the ARQ. In addition, when the first additional bits
113
are comprised of 8 zero bits, these first additional bits
113
can be used as tail bits for termination of the first ARQ block
104
-A.
Herein, the additional bits are comprised of 8 consecutive zero bits, and the number of the additional bits can be varied. As illustrated in
FIG. 1
, when a convolutional coder is used, the first additional bits
113
can be used for termination of the first ARQ block
104
-A. Even in the case where the ARQ block
104
is comprised of several sub ARQ blocks
104
-A and
104
-B, the additional bits can be used for termination. Since the first and second ARQ blocks
104
-A and
104
-B are independently terminated, it is possible to simultaneously decode the two sub ARQ blocks in parallel at a receiver. That is, in the convolutional coder, even though the subframe structure is used, the channel coding block and the ARQ block can be equal in size to each other because of the additional bits.
FIG. 2
illustrates another conventional layered frame structure, in which subframes are taken into consideration. Here, a turbo coder is used for a channel coder. In the frame of
FIG. 2
, turbo tail bits
223
are comprised of 8 bits, values of which are not consecutive zero bits but are varied according to feedback values from a recursive convolutional coder constituting the turbo coder. In
FIG. 2
, since a turbo interleaver existing in a channel coding block
103
performs turbo coding after scrambling the data of the whole ARQ block
104
, it is not possible to independently decode the sub ARQ blocks as in FIG.
1
. That is, in the turbo coder, even though the ARQ block
104
is comprised of several sub ARQ blocks, decoding should be performed at a time for the whole ARQ block to decode the data for each sub ARQ block. In this case, although the ARQ block
104
is segmented into sub ARQ blocks
104
-A and
104
-B, it is not possible to simultaneously decode the sub ARQ blocks in parallel a
Kim Jae-Yoel
Park Chang-Soo
De'cady Albert
Dilworth & Barrese LLP
Samsung Electronics Co,. Ltd.
Torres Joseph D.
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