Method to form dual damascene structure

Details Method to form dual damascene structure Method to form dual damascene structure

2002-02-12

2003-06-17

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06579791

ABSTRACT:

BACKGROUND OF THE INVENTION
A typical prior art via-first dual damascene process to form a dual damascene structure within a CVD low-k intermetal dielectric (IMD) layer includes: via formation (patterning and etching); formation of a protective layer at the bottom of the via; then trench formation (patterning and etching). Once the via is formed, the CVD low-k material is exposed along the via's sidewalls.
The article entitled “0.15 &mgr;m ArF Excimer Laser Lithography using Top Surface Imaging with High Contrast Silylation Agent B(DMA)DS”, T. Ohfuji and N. Aizaki, 1994 Symposium on VLSI Technology Digest of Technical Papers, pages 93 and 94, describes silylation with B(DMA)DS and applied to a 193 nm wavelength ArF laser.
The article entitled “CVD Photoresist Processes for Sub-0.18 Design Rules”, T. Weidman et al., 1998 Symposium on VLSI Technology Digest of Technical Papers, pages 166 and 167, describes a process for photoresist deposition for imaging a layer for 193 nm wavelength lithography.
SUMMARY OF THE INVENTION
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of forming dual damascene structures.
It is another object of an embodiment of the present invention to prevent interaction of CVD low-k material with the DUV photoresist during trench patterning.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a stop layer formed over a second low-k material layer formed over a stop layer formed over a first low-k material layer is provided. These layers are etched to form a via opening exposing a portion of the structure. A photoresist layer is formed over the second low-k material layer stop layer and filling the via opening. The photoresist layer having a treated upper portion including a central trench pattern area that is wider than, and substantially centered over, the via opening. The treated upper portion of the photoresist layer preventing any effects to the underlying photoresist layer so that the underlying photoresist layer does not deleteriously interact with the first or second low-k material layer. Removing: (
1
) the central trench pattern area of the upper treated portion of the photoresist and the photoresist under the central trench pattern area to form a trench pattern opening exposing a portion of the second low-k material layer stop layer under the removed central trench pattern area; and (
2
) the photoresist layer within the via opening while leaving a portion of the photoresist layer within the via opening overlying the portion of the structure that was exposed by the via opening. Transferring the trench pattern opening to the second low-k material layer stop layer and the second low-k material layer to form a trench substantially centered over the remaining via opening and completing the dual damascene opening.


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Wolf., (Silicon Processing for the VSLI Era, Lattice Press, vol. 2, pp. 194-195).*
Article entitled “0.15 &mgr;m ArF Excimer Laser Lithography using Top Surface Imaging with High Contrast Silylation Agent B(DMA)DS”, T. Ohfuji et al., 1994 Symposium on VLSI Tech. Digest of Tech. Papers, pp. 93-94.
Article entitled “CVD Photoresist Processes for Sub-0.18 Design Rules,” T. Weidman et al., 1998 Symposium on VLSI Tech. Digest of Technical Papers, pp. 166-167.

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