Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-28
2003-02-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06523150
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit design; more specifically, it relates to a method for designing a voltage partitioned wirebond package.
BACKGROUND OF THE INVENTION
In an effort to increase performance, lower power consumption and integrate several integrated circuit technologies on the same chip, the concept of voltage islands has been introduced into integrated circuit design.
The voltage island concept allows for one or more portions of an integrated chip (islands) to be powered by both a chip wide power source (V
DD
)and one or more additional, voltage island power sources (V
DDX
.) V
DDX
and V
DD
can be switched on and off by the user as the operation of the integrated circuit demands. However, integrated circuit chips are generally mounted to a next higher level of packaging. One widely used class of packages is wirebond packages.
A wirebond package for an integrated circuit chip having a voltage island (a voltage partitioned wirebond package) must be compatible with and capable of supporting the power distribution and noise requirements of the voltage island, while not violating the geometric constraints of the wirebond package technology. Such restraints include wirebond lengths and crossovers and limited pad counts in the proximity the voltage island. Additionally, wire runs from the voltage island to chip pads must not exceed pre-determined limits.
Present design methodology for voltage partitioned wirebond packages relies heavily on user intervention and trial and error approaches that are both costly and time consuming. An automated design methodology for voltage partitioned wirebond packages would greatly speed up the wirebond package design process and reduce costs.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method of designing voltage partitions in a package for a chip, comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
A second aspect of the present invention is a method of designing voltage partitions in a package for a chip, comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; creating a chip voltage island model; computing the voltage drop across power buses in the chip voltage island; assigning more chip power pads to the chip voltage island if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; adding conductive interconnects to the chip voltage island model to create a chip voltage island/package interconnect model; creating a package voltage island inductance model; analyzing electrical attributes of the combination of chip voltage island/package interconnect model and package voltage island inductance model; and assigning additional chip pads to the chip voltage island pads and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
A third aspect of the present invention is a computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for designing voltage partitions in a package for a chip, said method comprising the computer implemented steps of: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
A fourth aspect of the present invention is a computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for designing voltage partitions in a package for a chip, said method comprising the computer implemented steps of: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; creating a chip voltage island model; computing the voltage drop across power buses in the chip voltage island; assigning more chip power pads to the chip voltage island if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; adding conductive interconnects to the chip voltage island model to create a chip voltage island/package interconnect model; creating a package voltage island inductance model; analyzing electrical attributes of the combination of chip voltage island/package interconnect model and package voltage island inductance model; and assigning additional chip pads to the chip voltage island pads and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
A fifth aspect of the present invention is a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing voltage partitions in a package for a chip said method steps comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
A sixth aspect of the present invention is a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing voltage partitions in a package for a chip said method steps comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; creating a chip voltage island model; computing the voltage drop across power buses in the chip voltage island; assigning more chip power pads to the chip voltage island if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power
Buffet Patrick H.
Chiu Charles S.
Sun Yu H.
Do Thuan
Kotulak Richard M.
Schmeiser Olsen & Watts
Smith Matthew
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