Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-12-31
2003-12-09
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C714S724000, C365S200000, C324S073100
Reexamination Certificate
active
06661718
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a testing device for testing a memory, in particular a random access semiconductor memory having a multiplicity of memory cells associated with bit lines that can be connected to input/output lines leading out of the memory by a drive circuit. The testing device tests the memory by performing a plurality of individual tests in accordance with a test program. The invention also relates to a method for testing a memory and to a circuit arrangement having a multiplicity of circuits that will be tested, that are formed on a common substrate, and that are separated in a following fabrication step.
As memory cell arrays in semiconductor memories become larger and larger with generation changes taking place at increasing speed, memory capacity is expected to approximately quadruple very three years (for example from the 64 Mbit DRAM generation to the 256 Mbit DRAM generation). It is essential to test memory cells in semiconductor memories because under certain circumstances a single defective memory cell can lead to the total failure of the entire semiconductor memory. For this reason, in most semiconductor memories, redundant memory cells are provided which are addressed instead of the defective memory cells. However, it is necessary to test the operational capability of the entire memory, i.e. of each semiconductor memory cell, to be able to replace the memory cells that are identified as faulty with redundant memory cells if appropriate. Hitherto, testers were used, which make contact with the semiconductor chips while they are still in the composite wafer by placing small needles on the contact areas. There are also testers that make contact with the semiconductor chips when they are already housed or wired. After the tester makes contact with the semiconductor chips, all the memory cells of the memory cell array are tested. The addresses of the defective memory cells are stored externally (that is to say in the tester) and are used for redundancy evaluation after testing the operational capability. In this evaluation, redundant memory cells are assigned to the addresses of the defective memory cells.
Given the currently achieved sizes of memory cell arrays with storage capacities of 256 Mbit or 1 Gbit, testing the memory cells entails considerable costs that are proportional to the size of the memory and are thus related exponentially to the generation of the memory chip. The testing procedure requires greater time for each semiconductor memory produced. For the imminent 1 Gbit generation, it is estimated that the testing costs make up 30% of the entire production costs.
Because the hardware of the expensive testers has to be adapted with each new generation, which again signifies significant expenditure, attempts are being made to reduce the necessary tests to a minimum. Carrying out the tests on several chips simultaneously cannot be expanded any more using the customary testing of up to 64 memories because this approach is limited by the number of contact needles of the tester that can be placed on the chip. Even with a conceivable reduction of the contact needles that are required for the test and that are to be placed on the chip, the entire memory cell array would have to be tested by the tester on a cell-by-cell basis.
The data that has been acquired by the test, relating to the position and/or addresses of the defective memory cells, is evaluated after the test by the hardware and the software of the tester or by a further external device. Here, a redundancy analysis is carried out which assigns redundant memory cells to the addresses of the defective memory cells. This assignment data is subsequently buffered or fed directly to an element that “wires” the assignment onto the chip. This can be done using a laser beam that burns away tracks, using fuses or anti-fuses, or using other suitable means.
The test program is generally contained in the external tester in the form of a fixed circuit or is produced by means of programmable units at great cost. Changing the test program or the devices that carry out the test leads to very cost-intensive delays in mass production, which often entails a loss of time that can not be made up.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a testing device, a circuit configuration including a plurality of circuits that will be tested, and a method for testing a memory which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a testing device that can be used universally, i.e. that does not require any structural changes when used with various memory sizes (that is to say is independent of the size of the memory arrays to be tested) or memory types. It is an object to enable the testing device to be quickly adapted to a changing test program without having to perform structural interventions. It is also an object of the invention to reduce the test duration.
With the foregoing and other objects in view there is provided, in accordance with the invention, a testing device in combination with a substrate having a memory that will be tested. The memory includes a plurality of memory cells and the memory stores a test program. The memory is formed either in the substrate or on the substrate. The testing device includes an interpreter element that operates and tests the memory in accordance with the test program that is stored in the memory.
A testing device that operates in accordance with a test program is provided. The test program command codes of the testing device are stored in the untested memory cell array of the memory chip that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device per se no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program which is suitable for the respective chip type is stored as a variable code on the respective memory that will be tested. It is thus also possible to test various memory chip types with the same testing device. Rapid adaptation of the test programs for the memory chips is also possible without necessitating intervention in the testing device. It is thus no longer necessary to perform time-consuming changing of the testers and/or of the programs that control the testers or to store the programs again in the case of different memory types. Additionally, it is no longer necessary to change the circuits of the memory chips. The exponential growth in the testing time using the expensive testers and the associated costs are prevented. As a result of the new approach of the individually programmable and cost-effective testing device, all of the tests that relate to the memory cell array can also be carried out in a more detailed way. This constitutes a significant improvement in that the faulty chips or their fault sources can be analyzed more precisely. The testing device can be used flexibly and can be quickly adapted to a new test program without having to make structural changes to the circuits of the memory; this enables the overall time that is necessary for the testing to be reduced.
In accordance with an added feature of the invention, the testing device is formed on or in the substrate. As a result, the formation of external contacts using contact needles that would be placed on the substrate of the memory is advantageously no longer necessary. This minimizes the use of external equipment, or makes it superfluous, and testing while already in the composite wafer is made possible.
In accordance with an additional feature of the invention, a plurality of identical or independent memories are formed in the substrate. These memories will be separated after the test is concluded, and if appropriate, after action in accordance with the results of these tests have been taken. The advantage is that the wafer on or in which the individual memory chips are f
Ohlhoff Carsten
Pöchmüller Peter
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Viet Q.
Stemer Werner H.
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