Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-27
2003-12-09
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S530000
Reexamination Certificate
active
06660601
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for fabricating the device and more particularly relates to a semiconductor device including low resistance heavily doped regions and a method for fabricating the device.
Recently, the number of devices integrated for a semiconductor integrated circuit has been increasing steeply and MIS semiconductor devices have been downsized drastically. Thus, to suppress a short channel effect and increase the drivability thereof, a gate electrode has to have its resistance decreased and an extended heavily doped layer, which is defined under the edges of the gate electrode as parts of source/drain regions, needs to have its resistance decreased and its junction depth reduced. Hereinafter, a known method for fabricating a p-channel MIS semiconductor device including an extended heavily doped layer will be described with reference to
FIGS. 6A through 6D
.
FIGS. 6A through 6D
are cross-sectional views illustrating known process steps for fabricating an MIS semiconductor device including an extended heavily doped layer.
First, in the process step shown in
FIG. 6A
, a trench isolation film
52
is formed in parts of an n-type semiconductor substrate
51
to define an active region. Then, a gate electrode
54
of polysilicon is formed over the active region in the semiconductor substrate
51
with a gate insulating film
53
interposed between them. Thereafter, ions of boron as a p-type dopant
55
are implanted using the gate electrode
54
and the isolation film
52
as a mask to form an ion-implanted layer
56
as a prototype for an extended heavily doped layer.
Next, in the process step shown in
FIG. 6B
, the substrate is heated to an elevated temperature for a short time. Specifically, the substrate is subjected to a first rapid thermal annealing (RTA) process under the conditions including 900° C. and 10 sec., for example, to activate the dopant existing in the ion-implanted layer
56
. In this manner, an extended heavily doped layer
56
a
is formed.
Subsequently, in the process step shown in
FIG. 6C
, a silicon nitride film is deposited over the substrate under the conditions including 700° C. and 20 min., for example. Then, the silicon nitride film is etched anisotropically to form a sidewall
57
of silicon nitride on the side faces of the gate electrode
54
. Thereafter, ions of boron as a p-type dopant
58
are implanted into the substrate using the gate electrode
54
, sidewall
57
and isolation film
52
as a mask to form an ion-implanted layer
59
as a prototype for a heavily doped source/drain layer.
Then, in the process step shown in
FIG. 6D
, the substrate is subjected to a second RTA process under the conditions including 1100° C. and 0.5 sec., for example, to activate the dopant existing in the ion-implanted layer
59
. In this manner, the extended heavily doped layer
56
a
and a heavily doped source/drain layer
59
a
are defined.
In a known method, an MIS semiconductor device is fabricated in the following manner to improve its drivability; the boron ions
55
are implanted at a low accelerating voltage in forming the ion-implanted layer
56
so that the extended heavily doped layer
56
a
has a shallow junction depth. Further, in forming the ion-implanted layer
56
by this process, the implant dose of the boron ions
55
is set as high as possible to decrease a parasitic capacitance produced between the extended heavily doped layer
56
a
and heavily doped source/drain layer
59
a.
However, the MIS semiconductor device obtained by the known method has the following drawbacks.
Firstly, we found that if a dopant was implanted as much as possible to reduce the resistance of the extended heavily doped layer, the resistance rather increased in the final structure.
Secondly, we also found that after the structure had gone through many process steps succeeding the second RTA process, the junction depth of the extended heavily doped layer had increased very much in the resultant MIS semiconductor device. The greater the junction depth, the more likely punch-through or short channel effect occurs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to clarify why those unfavorable phenomena occur and thereby provide a semiconductor device including low resistance heavily doped regions and a method for fabricating the device.
An inventive semiconductor device includes at least one heavily doped region that has been formed by introducing a dopant into a semiconductor layer. A maximum concentration of the dopant existing in the heavily doped region is at least greater than a predetermined percentage of a solid solubility of a first annealing process for activating the dopant and equal to or less than a solid solubility of a second annealing process that needs to be performed at the highest temperature after the dopant has been introduced into the semiconductor layer by an ion implantation process.
According to the present invention, almost all of a dopant existing in the heavily doped region can be activated. Thus, it is possible to suppress the heavily doped region from having its resistance increased by the deactivation (e.g., clustering or precipitation) of the dopant. As a result, a low resistance semiconductor device can be obtained. Further, the dopant may be introduced for an inventive semiconductor device at a dose lower than the dose for a known semiconductor device. Therefore, the junction depth of the dopant can be reduced and a semiconductor device with high drivability can be obtained.
In one embodiment of the present invention, almost all of the dopant existing in the heavily doped region has preferably been activated.
In another embodiment, the maximum concentration of the dopant may be 90 to 100% of the solid solubility at a process temperature of the first annealing process. In such an embodiment, almost all of the dopant can be activated through the first annealing process. Thus, no inactive dopant atoms will newly deactivate the activated dopant atoms even if annealing processes are carried out at low temperatures for a long time after that. Accordingly, the dopant can be activated with more certainty.
In an alternative embodiment, the maximum concentration of the dopant may be greater than the solid solubility at a process temperature of the first annealing process and may be 90 to 100% of the solid solubility at a process temperature of the second annealing process. Then, the heavily doped region may contain the dopant at the highest possible concentration that the second annealing process can cope with.
In still another embodiment, the inventive semiconductor device may include: a gate electrode, which has been formed over the semiconductor layer with a gate insulating film interposed between the gate electrode and the semiconductor layer; an extended heavily doped layer, which has been defined as the heavily doped region in parts of the semiconductor layer that are located beside the gate electrode; a sidewall, which has been formed on the side faces of the gate electrode; and a heavily doped source/drain layer, which has been defined in parts of the semiconductor layer that are located beside the sidewall to surround the outer periphery of, and be in contact with, the extended heavily doped layer, and which has a junction deeper than the junction of the extended heavily doped layer.
In yet another embodiment, the semiconductor layer may be a gate electrode of polysilicon and the gate electrode may include the heavily doped region. Then, an MIS semiconductor device can have its resistance reduced.
An inventive method for fabricating a semiconductor device includes the step of a) introducing a first dopant into at least part of a semiconductor layer by an ion implantation process, thereby forming a first ion-implanted layer in the part. The method further includes the step of b) subjecting the first ion-implanted layer to a first annealing process. And the method further includes the step of c) subjecting the semiconductor layer
Akamatsu Susumu
Matsumoto Michikazu
Miyata Satoe
Umimoto Hiroyuki
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
Thomas Toniae M.
Wilczewski Mary
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