Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-12
2003-12-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S200000, C438S303000
Reexamination Certificate
active
06660602
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a snapback ESD protection structure. In particular it relates to a protection structure for CMOS and BiCMOS ICs used in high voltage applications, such as over-voltage I/O cells and power supplies:
BACKGROUND OF THE INVENTION
In the case of high voltage CMOS and BiCMOS circuits such as I/O cells and power supplies, grounded gate NMOS snapback devices are commonly used for electrostatic discharge (ESD) protection. In fact, in 80% to 90% of CMOS applications, snapback NMOS structures are the protection solution used. It is common to include either separate, stand-alone ESD protection devices for channeling high ESD currents to ground, or to create self-protecting I/O cells in which the same device is used as a high current output driver as well as for ESD protection.
In order to appreciate the respective benefits of self-protection structures as compared to stand-alone protection, it is useful to consider the attributes of NMOS snapback structures. Typically NMOS clamps work adequately during pulsed ESD operation but experience difficulties at continuous excessive currents or very high currents due to limited energy dissipation capability. NMOS snapback structures operate using avalanche multiplication of charge carriers to create conductivity modulation in the on-state.
FIG. 1
shows a cross-sectional view that illustrates a conventional NMOS device. As shown in
FIG. 1
, NMOS
100
has gates
102
,
104
formed on a p-type semiconductor material
106
. Considering only the NMOS device defined by the gate
104
,
FIG. 1
, further, shows a n-doped drain
110
and n-doped source
112
extending along the sides of the gate
104
. In operation, when the voltage across the drain
110
and source
112
is positive but less than the trigger voltage the voltage reverse biases the junction between the p-material under the gate
104
and the n-type material of the drain
110
and source
112
. The reverse-biased junction block charge carriers from flowing from drain to source in the absence of appropriate biasing of the gate. However, when the voltage across the drain
110
and source
112
is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication causing holes to be injected into the region beneath the gate
104
. The increased number of holes increases the potential of the material beneath the gate
104
and eventually forward biases the junction between the gate and the source, causing the holes to be swept across the junction to be collected by the source
112
. Similarly, electrons are swept across from the source to the drain. Some of the electrons injected into the region below the gate
104
recombine with holes and are lost while another part of the holes is lost through the substrate contact. The limited energy dissipation capabilities of NMOS ESD protection clamps can be attributed to the extremely localized region for heat dissipation, which corresponds to approximately a 0.5 &mgr;m region near the gate-drain region.
This becomes even more significant in the case of overvoltage cells that make use of cascoded structures to increase the operating voltage (for example to increase the operating voltage from 3.3 V to 5V.) The double gates of the cascoded structure result in a larger drain-source spacing, as is evident from FIG.
1
. When the structure is connected as a set of two cascoded devices with a dual gate, the gates
102
and
104
serve as the gates of the cascoded structure, and the region
120
acts as the source, with the region
110
serving as the drain. However, in such a structure the drain-source spacing between the drain
110
and source
120
is considerably greater. For instance, in a 0.18 &mgr;m CMOS dual gate oxide process, the spacing will be approximately 1.2 &mgr;m. This causes more charge carriers to be lost instead of being swept across the junction. Consequently, a higher electric field is required for avalanche multiplication. The resultant higher electric field E, lattice temperature, and input ionization at the gate
104
exposes the region along the edge of the gate
104
to higher soft gate leakage current degradation and hot carrier degradation.
In the case of high voltage applications such as over-voltage circuits, the use of a stand-alone structure or clamp for channeling current to ground during an ESD event would therefore help avoid the high electric fields and temperatures in the cascoded I/O or power supply structure. However, this exposes the clamp itself to the electric fields and temperatures that the cascoded structure is being protected from. The high potential difference across the source and drain of the NMOS clamp also results in a substantial amount of leakage current which becomes particularly significant in the case of long structures used in high voltage applications.
One solution that could be adopted is to make use of a Thick Field Oxide (TFO) device in which a shallow trench isolation region
200
separates the drain
210
from the source
212
, as shown in FIG.
2
. However, the shallow trench isolation region
200
is not entirely effective at avoiding leakage current, and, more significantly, displays a high breakdown voltage.
The present invention seeks to provide a stand-alone structure that has both a low breakdown voltage while providing good leakage isolation. Furthermore, the present invention provides a structure that is more robust to the effects of gate soft leakage degradation and hot-carrier degradation of the gate region.
SUMMARY OF THE INVENTION
The present invention provides a new stand-alone NMOS ESD protection structure in which the high junction potential is shifted away from the gate region of the device to separate the electrical stress region with its high electric field, impact ionization, and lattice temperature (which is normally most prevalent at the gate corner) away from the gate region, while still retaining the reduced leakage current provided by the NMOS structure. The gate is preferably grounded or has a low bias voltage to keep the potential drop across the junction between the n+ source and the p-substrate low. The n+ drain to p-substrate junction thus defines a bipolar surface device which provides a low breakdown voltage.
According to the invention there is provided a NMOS structure and a method of creating the NMOS structure in which the n-lightly doped drain (NLDD) and n+ regions of the drain are blocked near the gate to shift the p-n junction away from the gate and create a space between the gate and the drain junction. Preferably the NLDD is fully blocked while the n+ region is partially blocked.
Further, according to the invention, there is provided a method of reducing the breakdown voltage of a NMOS device, comprising at least partially blocking the NLDD and n+ region of the drain. The n+ region preferably defines a sharp surface junction with the p-well or p-substrate material.
Further, according to the invention, there is provided a method of reducing hot carrier degradation in a NMOS device, comprising reducing the potential differences across junctions near the gate by keeping the potential difference across the junction between the n+ source and p-well or substrate low, and by shifting the junction between the n+ drain and the p-well or substrate away from the gate. Preferably the device is a grounded gate NMOS (GGNMOS) device to keep it at the same potential as the grounded well or substrate.
Still further, according to the invention, there is provided a method of reducing the holding voltage of a NMOS device, comprising blocking at least part of the NLDD to leave a drain-substrate junction that is solely between the n+ drain region with its higher injection coefficient and the p-well.
REFERENCES:
patent: 6465311 (2002-10-01), Shenoy
Beek Marcel ter
Concannon Ann
Hopper Peter J.
Vashchenko Vladislav
Elms Richard
National Semiconductor Corp.
Owens Beth E.
Vollrath & Associates
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