Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-25
2003-10-28
Kielin, Erik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C438S587000, C438S595000
Reexamination Certificate
active
06638829
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductor structures and, more particularly, to a metal gate electrode formed in combination with elevated salicided source/drain regions.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
A typical MOS semiconductor device generally includes a gate electrode, which acts as a conductor, to which an input signal is typically applied via a gate terminal. Heavily doped source/drain regions are formed in a semiconductor substrate and are respectively connected to source and drain terminals. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The channel is typically lightly doped with a dopant type opposite that of the source/drain regions. The gate electrode is physically separated from the semiconductor substrate by a gate insulating layer, typically an oxide layer such as SiO
2
. The insulating layer is provided to prevent current from flowing between the gate electrode and the source/drain regions or channel region.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source region/drain regions. In this manner an electric field controls the current flow through the channel region. This type of device is commonly referred to as a MOS field-effect transistor (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate ever increasing numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) and in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered.
Several objectives influence MOSFET design and fabrication. First, there is a desire to reduce the dimensions of the MOSFET. Increasing the number of individual MOSFETs that can be placed onto a single silicon chip or die produces increased functionality per chip. Second, there is a continual desire to improve performance, and particularly the speed, of the MOSFET transistors. This pursuit is manifested in shorter conduction channel lengths and in efforts to obtain low contact resistivity at the MOSFET junctions. These aspects offer increased MOSFET speed and allow for a greater number of operations to be performed by the MOSFET in less time. MOSFETs are used in great quantity in computers where the push to obtain higher operation cycle speeds demands faster MOSFET performance. Lastly, there exists a constant need to minimize costly MOSFET fabrication steps.
Many prior MOSFETs designs have metal gate electrodes. However, with the challenges that accompany sub-micron gate alignment and modern high-temperature processing, metal gate electrodes have often been replaced with polysilicon gate electrodes. One difficulty faced in making semiconductor structures having metal gates is that the melting point of the metal is below the temperatures applied to the structure during high temperature thermal annealing which is used for various purposes during fabrication. Polysilicon, in contrast, has a much higher melting point. Thus, polysilicon is often used for gate electrodes. However, metal is desirable because of its conductivity and its ability to produce a stronger electric field.
Conventional approaches have encountered difficulty trying to maintain performance in the face of decreasing size and increasing density of devices. In attempting to overcome these hurdles, it is equally desirable to keep costly processing steps to a minimum. Therefore, it is desirable to provide a semiconductor structure and provide a process for its manufacture to address the above identified problems.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a semiconductor structure and a process for its manufacture. In one embodiment, a semiconductor structure is provided. The semiconductor structure comprises a metal gate electrode formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions.
In another embodiment, a process is provided for manufacturing a semiconductor structure. The process comprises forming a polysilicon alignment structure on a semiconductor substrate. A first concentration of a first dopant species is implanted at a first energy level into the substrate, whereby lightly doped drain regions are formed in the substrate and aligned with the alignment structure. Nitride spacers are formed on sides of the alignment structure, and a second dopant species is implanted into the substrate at a second energy level and a second concentration, whereby source and drain regions are formed in the substrate and aligned with the alignment structure. An epitaxial layer is grown on the substrate adjacent to the spacers, and the polysilicon alignment structure is removed, thereby forming a trench between the spacers. A gate dielectric is formed in the trench, and a silicide layer is formed on the epitaxial layer. Lastly, a metal gate electrode is formed in the trench.
REFERENCES:
patent: 5168072 (1992-12-01), Moslehi
patent: 5198378 (1993-03-01), Rodder et al.
A. Chatterjee et al. “Sub-100nm Gate Length Metal Gates NMOS Transistors Fabricated by a Replacement Gate Process”, IEDM, pp. 821-824, Dec. 1997.*
Stanley Wolf, Silicon Processing for the VLSI Era, Vo. 2: Process Integration, pp. 144-151, 157-158, 1990.*
R. D. Butler, “MOS Fabrication Process Integrating Self-Aligned Polysilicon Gate and Post-Processed Metal Gate Devices on a Single Die” University/Government/Industry Microelectronics Symposium, pp. 199-203, Jun. 1991.
Cheek Jon
Gardner Mark I.
Wristers Derick
Advanced Micro Devices , Inc.
Kielin Erik
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