Channelled chamber surface for a semiconductor substrate...

Coating apparatus – Gas or vapor deposition

Reexamination Certificate

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Details

C118S728000, C118S7230IR, C156S345510, C156S345300, C156S345290

Reexamination Certificate

active

06656283

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The present invention relates generally to semiconductor substrate processing systems and, more particularly, the invention relates to a chamber surface for a semiconductor substrate processing chamber having particle collection channels formed in the surface.
2. Description of the Background Art
In modem fabrication of integrated circuits, features are formed on semiconductor substrates, often silicon wafers, by processing the substrates in enclosed processing chambers, often within a multichamber processing system. Typically, a substrate is robotically introduced into a chamber and secured to a support member, or pedestal, within the chamber. As part of the processing procedure, the processing surface of a substrate may be exposed to gas introduced through a gas inlet and later expelled through a gas outlet, the inlet and outlet being formed in the walls of the chamber.
Various types of processing chambers are used to process semiconductor substrates. In a deposition chamber, layers of material are deposited on the processing surface of a substrate that is secured to a support member. Deposition chambers include physical vapor deposition (PVD) chambers and chemical vapor deposition (CVD) chambers. In PVD chambers, particles are typically sputtered from a target to form layers of material on the processing surface of a substrate. In CVD chambers, introduced gas or gases are used to cause chemical reactions, the product of which deposits on the processing surface of a substrate, forming layers thereon. In an etch chamber, features are formed by chemically removing material from the surface of a substrate by exposing the surface to an etchant gas or gases introduced into and later expelled from the chamber. In a plasma enhanced etch chamber, such as a decoupled plasma source (DPS) etch chamber, a plasma is generated within the chamber above the processing surface of the substrate. During the course of a number of processing steps, plasma generation may be cycled on and off a number of times.
One persistent problem encountered in various types of processing chambers including PVD, CVD and etch chambers is that particles can be generated in the chamber and cause unwanted deposits on various components within the chamber and on the substrate itself. Unwanted particles in the chamber can contaminate the processing surface of a substrate, causing waste and inefficiency.
In plasma enhanced etch chambers, unwanted particle formation within the chamber is practically inevitable. Material removed from the processing surface of the substrate can cause unwanted deposition on surfaces within the chamber before the etchant gas containing the particles can be exhausted. In addition, the plasma can cause chemical reactions and particle film accumulation on surfaces within the chamber, which can eventually crack or flake and generate particles that contaminate the chamber environment and can ultimately deposit on the processing surface of the substrate. When the plasma is cycled off, particles in the chamber environment may settle on surfaces within the chamber, such as the bottom of the chamber, only to be lifted again when gases are flowed into the chamber and the plasma is next cycled on, increasing the chances that the particles will contaminate the processing surface of the wafer.
Avoiding the presence of unwanted particles within the chamber is a difficult problem. Various methods of reducing unwanted particulate contamination and deposition in processing chambers are presently utilized. In etch chambers, unwanted deposition can in some cases be reduced by the use of self-cleaning chemistries. This involves introducing chemical agents, such as fluorine- or chlorine-based compounds, into the chamber that reduce unwanted deposition by reacting with and eliminating the unwanted deposits.
Another approach in reducing the amount of contaminant particles present in the chamber environment involves taking steps to increase adhesion of particles to the chamber walls, thus trapping some of the particulate material so that it cannot contaminate the substrate. This can be accomplished by keeping the chamber walls cool or the surfaces of the walls rough, in order to increase adhesion. This approach has the disadvantage of causing deposits to build up on the walls of the chamber. As these deposits accumulate, thermally induced stresses within the chamber can eventually cause them to crack or flake off, shedding particles that contaminate the chamber environment. Further, causing adhesion of particles to the chamber walls is especially difficult in silicon etch chambers, where the wide and unpredictable variety of particles generated causes difficulty in selecting an ideal type of surface to promote particle adhesion.
Controlling the temperature of the chamber components can sometimes be used to reduce unwanted particulate contamination and deposition within a chamber, depending on the type of chamber and processing circumstances. However, temperature control is at best a partial solution and can be difficult to achieve, particularly considering the difficulty in thermally isolating chamber components during processing steps that require heating the substrate.
Removable chamber liners are sometimes used to remove unwanted depositions within the chamber. However, using liners requires frequently removing and replacing contaminated liners. In addition, accumulation of particles within the chamber between changes of the liner remains a problem.
As discussed above, while various approaches are presently employed to reduce particulate contamination within a chamber and unwanted deposition on the substrate, none of the approaches provide a completely effective solution.
Therefore, there is a need for processing chamber-related equipment that can reduce the amount of particles present in a chamber.
SUMMARY OF THE INVENTION
The present invention generally provides a chamber surface for a semiconductor substrate processing chamber having particle collection channels formed in the surface. Particles in the chamber are trapped in the channels and thereby prevented from contaminating chamber components or a processing substrate.
In one embodiment, the invention provides a liner for the bottom of a plasma etch chamber. Channels formed in the liner lead from an area near a support member to an opening leading to a gas outlet. The channels are sized to prevent plasma from entering the channels and potentially lifting trapped particles out of the channels. Gas flow within the chamber drives particles collected in the channels in the direction of the gas outlet until they are removed through the gas outlet by a vacuum pump. The liner may also have recesses in addition to the channels, to further trap particles and prevent them from contaminating the substrate. Additionally, secondary channels, or tributaries, may be formed in the liner, each tributary connecting to a channel and radiating outwardly therefrom. Particles trapped in the tributaries are driven by gas flow into the channels, where the particles are further driven to the gas outlet.
In another embodiment, the invention provides a chamber liner having a sidewall, with particle collection channels formed in the sidewall and sized to prevent plasma from entering the channels and potentially removing the particles.
In another embodiment, the invention provides a chamber having a plurality of particle collection channels formed in a chamber bottom. Tributaries and/or recesses may also be formed in the chamber bottom.
In still another embodiment, the invention provides a chamber having a plurality of particle collection channels formed in a chamber sidewall.


REFERENCES:
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patent: 5891350 (1999-04-01), Shan et al.
patent: 5935334 (1999-08-01), Fong et al.
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patent: 6093281 (2000-07-01), Wise et al.
patent: 6176969 (2001-01-01), Park et al.
patent: 6251216 (2001-06-01), Okamura et al.
patent: 6447853 (2002-09-01), Suzuki et al.

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