Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2001-04-13
2003-02-11
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S787000, C257S723000, C257S773000
Reexamination Certificate
active
06518654
ABSTRACT:
TECHNICAL FIELD
The disclosure pertains to packages for semiconductor die and methods of packaging semiconductor die.
BACKGROUND
Semiconductor fabrication processes have been developed that permit the integration of very large numbers of transistors, diodes, and other circuit elements onto a single integrated circuit. Such integrated circuits generally require large numbers of electrical connections to receive inputs and supply outputs. Because these integrated circuits are generally very small, the required input/output electrical connections on the integrated circuit are both numerous and densely spaced.
A significant problem in the use of integrated circuits is packaging the integrated circuit in such a way as to electrically connect to the many, densely spaced input/output electrical connections. If the input/output electrical connections must be spread out to permit electrical connections to other integrated circuits, other circuits or circuit components such as printed circuit boards, then much of the advantage of integrated circuit miniaturization is lost.
One method of packaging integrated circuits for electrical connection to a printed circuit board is the so-called ball grid array (BGA) package. A BGA package includes a semiconductor die (an integrated circuit) that is attached to a substrate. Electrical connections are made from the die to the substrate with bond wires that are attached to bond pads provided on the die and the substrate. The bond pads on the substrate are electrically connected to an array of solder balls or bumps, and these solder balls are used to bond and make electrical connection the printed circuit board. BGA packages are described in, for example, Tsuji et al., U.S. Pat. No. 5,930,603, Tsunoda et al., U.S. Pat. No. 5,914,531, and Tsuji et al., U.S. Pat. No. 5,293,072.
Not only are BGA packages more compact than other packages, BGA packaged devices generally have superior thermal and electrical properties. The solder balls provide an excellent thermal path for the removal of heat from the semiconductor die as well as providing low resistance, low inductance electrical connections.
BGA packages have several drawbacks. For example, soldering a BGA packaged device to a printed circuit board can require precise soldering process control. Accordingly, improved packages, packaging methods, and packaging apparatus are needed.
SUMMARY OF THE INVENTION
Packaged semiconductor die are provided that include a semiconductor die attached to a first major surface of a substrate. One or more solder bumps or balls are attached to a second major surface of the substrate opposite to the first major surface. A substrate edge extends between the first and second major surfaces. An elongated rib projects outwardly from the second major surface and extends along at least part of a perimeter portion of the second surface. In some embodiments, the rib overlaps and encapsulates at least a portion of the substrate edge. The rib may comprise a band or frame that borders the entire perimeter of the second surface of the substrate. The field or space within the frame may comprise a void or recess bounded by the frame and second surface of the substrate and which is void of material except for solder bumps within the recess.
In additional embodiments, packaged die include a package cover that encapsulates at least a perimeter portion of the first surface of the substrate and the semiconductor die. Some embodiments includes bond wires that electrically connect the semiconductor die to the substrate, and the package cover encapsulates the bond wire. In other embodiments, the packaged semiconductor die includes an adhesive layer that bonds the semiconductor die to the first surface of the substrate.
Integrated circuit assemblies are provided that include a semiconductor die that is attached and electrically connected to a substrate. Solder bumps electrically connect the substrate to a circuit board and a package cover encapsulates the semiconductor die and at least a portion of an edge of the substrate. The package cover includes a rib that extends to contact the circuit board.
Mold sets are provided for molding a package for at least one die bonded to a substrate. The mold sets include an upper mold and a lower mold. The upper mold defines a package cover for encapsulating the die and a portion of a surface of the substrate to which the die is bonded while the lower mold defines a rib that extends from a surface of the substrate. In a specific embodiment, the upper mold and lower mold define the package cover and the rib so that a portion of the substrate edge is encapsulated by either the package cover or the rib, or both the package cover and the rib. In additional embodiments, the upper mold and the lower mold define package covers and ribs for a plurality of die bonded to the substrate such as a substrate strip.
Methods of reducing moisture penetration into a circuit assembly that includes a substrate and a circuit board are provided that include covering at least a portion of an edge of a substrate with an encapsulant. In addition, a rib may be formed that covers at least a portion of a first surface of the substrate and extends from a second surface of the substrate and contacts the circuit board. In further embodiments, the circuit assembly includes a die and the die is covered with the encapsulant.
Methods of soldering a substrate provided with solder bumps to a circuit board are provided. The methods include contacting the circuit board with the solder bumps and heating the solder bumps so that the solder bumps reflow, thereby connecting the solder bumps to the circuit board. A projecting stop is situated along at least a portion of the periphery to maintain a separation between the substrate and the circuit board as the solder bumps reflow. In some embodiments, the solder bumps are heated so that the stop contacts the circuit board and the stop is bonded to the circuit board and the substrate. The stop may comprise an elongated rib which projects from the surface of the substrate containing the bumps. Typically an elongated portion of the stop is positioned along each side of the periphery of the substrate to maintain the desired spacing.
Methods of packaging a die are provided that include bonding the die to a first surface of a substrate and attaching one or more solder bumps to a second surface of the substrate. In addition, an encapsulating layer is provided that encapsulates the die, wherein the encapsulating layer includes a rib that encapsulates at least a perimeter portion of the second surface of the substrate. In some embodiments, the encapsulating layer encapsulates at least a portion of the first surface of the substrate and the rib is defined with a mold. In other embodiments, the rib has a thickness that is at least as large as a thickness of the solder bumps.
Methods of attaching a substrate to a circuit board are provided that include providing a rib that covers a perimeter portion of a surface of a substrate and electrically connecting the substrate to the circuit board so that the separation of the substrate and the circuit board is defined by the rib.
Methods of attaching a ball grid array packaged die to a circuit board are provided that include providing a support rib at a perimeter of a surface of the ball grid array packaged die and heating the packaged die to reflow solder bumps provided at the surface.
Methods of making a package for a die mounted to a substrate are provided that include contacting a first surface of the substrate with a first mold and contacting the first mold with a second mold. An encapsulant is injected into a cavity defined by the first mold and the second mold, wherein one of the first mold and the second mold define a cavity for a rib.
The invention is directed to novel and non-obvious aspects of this disclosure, both individually and in combination as set forth in the claims below.
REFERENCES:
patent: 4641176 (1987-02-01), Keryhuel et al.
patent: 5293072 (1994-03-01), Tsuji et al.
patent: 5448114 (1995-09-01), Kon
Baerlocher Cary J.
Bolken Todd O.
Cobbley Chad A.
Corisis David J.
Clark Jasmine J B
Klarquist & Sparkman, LLP
Micro)n Technology, Inc.
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