Method to fabricate poly tip in split gate flash

Details Method to fabricate poly tip in split gate flash Method to fabricate poly tip in split gate flash

2000-09-05

2003-10-21

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S321000

Reexamination Certificate

active

06635922

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a poly tip in split-gate flash cells.
(2) Description of the Related Art
Programming (coding) and erasing (decoding) of memory cells is accomplished by tunneling of electrons through the thin oxide between the substrate and the floating gate in a split-gate flash memory cell. The effectiveness of the program/erase modes, that is, the speed with which they can be performed, can be enhanced by providing a protrusion for the floating gate of the split-gate cell. Normally, the protrusion is formed by poly oxidation, that is, by oxidizing the polysilicon of which the floating gate comprises; That is, the oxidized portion of the poly-gate is used as a hard mask to form a protruding, so-called gate bird's beak (GBB), or, a tip, which in turn enhances the well-known Fowler-Nordheim (F-N) tunneling for the programming and erasing of an EEPROM cell. However, thick poly is needed in order to grow a thick poly-oxide hard-mask. Thick poly, on the other hand, increases gate coupling ratio (GCR), a parameter which is well-known in the art. Increased GCR then degrades the programming and erasing function of the cell. Especially, with the fast pace of miniaturization and scaling down of devices, it s becoming more and more difficult to form thick poly-oxides because of the oxide thinning effect.
Furthermore, the forming of a GBB must be optimized carefully, for, otherwise, the GBB can encroach under the gate edge and degrade the programmability of submicron memory cells. That is, the dimensions and shape of the GBB, which is described below more in detail in relation to nonvolatile memories, play an important role in transferring current to and fro between the substrate and the floating gate, and hence the charging speed of the memory cell, and the amount of surface current leakage that takes place around and near the bird's beak. It is disclosed in this invention a method of forming a poly tip, in place of the conventional GBB, by forming a tapered floating poly-gate, whereby the tip is more controllable and sharper and therefore the program/erase mode of the split-gate flash memory cell is more enhanced.
The shape and size of different portions of memory cells have different effects on the performance of the memory cells in different ways. Thus, with the one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. Another variation which is disclosed in this invention relates to the tapered shape of the edge of the floating gate which significantly affects the erase speed of split-gate flash memory cells.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG.
1
. The forming of the cell is shown in
FIGS. 2
a
-
2
f
which will be described shortly. In the final form of the cell shown in
FIG. 1
, There, a MOS transistor is formed on a semiconductor substrate (
10
) having a first doped region (
1
), a second doped region (
9
), a channel region (
5
), a gate oxide (
11
), a floating gate (
12
), intergate dielectric layer (
15
) and control gate (
16
). Substrate (
10
) and channel region (
5
) have a first conductivity type, and the first (
1
) and second (
9
) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in
FIG. 1
, the first doped region, (
1
), lies within the substrate. The second doped region, (
9
), lies within substrate (
10
) and is spaced apart form the first doped region (
1
). Channel region (
5
) lies within substrate (
10
) and between first (
1
) and second (
9
) doped regions. Gate oxide layer (
11
) overlies substrate (
10
). Floating gate (
12
) covered by poly-oxide (
14
), and to which there is no direct electrical connection, and which overlies substrate (
10
), is separated from substrate (
10
) by a thin layer of gate oxide (
11
) while control gate (
16
), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (
15
) therebetween.
In the structure shown in
FIG. 1
, control gate (
16
) overlaps the channel region, (
7
), adjacent to channel (
5
) under the floating gate, (
12
). This structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (
7
) determines the cell performance. Furthermore, the shape of the edge (
3
) and, in particular, that of edge (
13
) can affect the programming of the cell. It is disclosed in this invention that the edge (
13
) can be shaped differently to have a sharp and robust tip. This is accomplished by forming a tapered floating gate as disclosed later in the embodiments of the present invention.
To program the transistor shown in
FIG. 1
which shows the placement of gate, source and drain voltages or Vg, V
s
and V
d
, respectively, charge is transferred from substrate (
10
) through gate oxide (
11
) and is stored on floating gate (
12
) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” of “off.” “Reading” of the cell's state is accomplished by applying appropriate voltages to the cell source (
1
) and drain (
9
), and to control gate (
16
), and then sensing the amount of charge on floating gate (
2
). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This, programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold v

Affiliated with

Also associated with

Rating

Method to fabricate poly tip in split gate flash does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to fabricate poly tip in split gate flash, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to fabricate poly tip in split gate flash will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3132443