Method of fabricating FET or CMOS transistors using MeV implanta

Details Method of fabricating FET or CMOS transistors using MeV implanta Method of fabricating FET or CMOS transistors using MeV implanta

1995-06-07

1998-10-13

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438303, 438306, 438307, 438199, H01L 21336

Patent

active

058211462

ABSTRACT:
A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.

REFERENCES:
patent: 4764477 (1988-08-01), Chang et al.
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5489540 (1996-02-01), Liu et al.
patent: 5491099 (1996-02-01), Hsu
patent: 5504023 (1996-04-01), Hong
patent: 5512506 (1996-04-01), Chang et al.
patent: 5595919 (1997-01-01), Pan

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